The dependability deficiencies and bandwidth constraints of the controller area network (CAN) can prevent its use in safety-relevant and performance-demanding applications. This paper introduces mechanisms for fault detection and fault isolation based on an intelligent CAN router, which exploits a priori knowledge about the permitted behavior of attached electronic control units (ECUs) in order to detect and contain failures. Experiments using an FPGA-based implementation of the CAN router evaluate these mechanisms under different failure modes (e.g., timing failures, masquerading failures). Due to its compatibility to the CAN standard, the router can improve the dependability and performance of systems with existing ECUs. In addition, we extend the application areas of CAN to systems with higher performance and dependability requirements than can be supported with a conventional bus-based network.

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Abstract-Controller Area Network (CAN) provides an inexpensive and robust network technology in many application domains. However, the use of CAN is constrained by limitations with respect to fault isolation, bandwidth, wire length, namespaces and diagnosis. This paper presents a solution to overcome these limitations by replacing the CAN bus with a star topology. We introduce a CAN router that detects and isolates node failures in the value and time domain. The CAN router ensures that minimum message interarrival times are satisfied and reserves CAN identifiers for individual CAN nodes. In addition, the CAN router exploits knowledge about communication relationships for a more efficient use of communication bandwidth through multicast messaging. An implementation of the CAN router based on a Multi-Processor System-on-a-Chip (MPSoC) shows the feasibility of the proposed solution.

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In this paper we address the problem of improving the instruction cache performance for single-path code. The properties of single-path code allow us to align single-path loops within the cache in order to reduce the number of cache misses during the loop execution. We propose an algorithm that categorizes loops in a simple way so that the loops can be aligned and NOP instructions can be inserted to support this loop alignment. Our experimental results show the predictability for cache misses in single-path loops and demonstrate the benefit of the single-path loop alignment.