We present an anomalous latchup failure phenomenon related to the large Nwell resistor associated with the generic RC-triggered, MOSFET-based Active Clamp circuit for on-chip ESD protection between VCC and VSS buses. A novel Active Clamp circuit with PMOS feedback technique has been proposed to reduce the IC's susceptibility to Latchup during negative current injection at neighboring 1 1 0 pads or false triggering of the RC trigger circuit due to noise on the VCC power line. The effectiveness of this new Active Clamp circuit is confirmed by our experiment and simulation results.

The on-chip Transient Voltage Suppressor (TVS) embedded in the silicon based transceiver IC has been proposed in this paper by using 0.8 μm Bipolar-CMOS-DMOS (BCD) process. The structure of the on-chip TVS is a high voltage Dual Silicon-Controlled-Rectifier (DSCR) with ±19V of high holding voltage (Vh) under the evaluation of 100ns pulse width of the Transmission Line Pulsing (TLP) system. The holding current (Ih) of the on-chip TVS is so high that can pass ±200mA latchup testing. Therefore, the on-chip TVS can be safely applied to protect the ±12V of signal level for RS232. The RS232 transceiver IC with on-chip TVS has been evaluated to pass the IEC61000-4-2 contact ±12kV stress without any hard damages and latchup issue. Moreover, the RS232 transceiver IC also has been verified to well protect the system over the IEC61000-4-2 contact ±20kV stress (CLASS B) in the smart scanner and notebook application Index Terms-ESD, RS232, SCR, TVS