To realize next-generation highly realistic sensation broadcasting systems, the research and development of 8K ultrahigh-definition television (UHDTV) systems have been promoted. To realize 8K video cameras, 33Mpixel sensors [1-2] and a full-resolution camera system that uses three 33Mpixel sensors [3] have been reported. However, the weight of the camera with three sensors is over 40kg because the camera requires a large-format color-separation prism. To reduce the size of the camera, single-chip imaging is a promising approach, and a compact single-chip 8K camera that weighs only 2kg has already been developed using a color 33Mpixel CMOS image sensor [4]. However, a conventional single-chip camera has a lower image quality than a full-resolution camera because the total pixel count of the single-sensor camera is only one-third of that of the three-sensor camera, and pixel interpolation is required to configure a full-resolution image. In this paper, a 133Mpixel sensor that can be operated at 60fps to realize a full-resolution 8K single-chip camera is described. To achieve both high speed and suitable ADC resolution, 32-column multiplexing analog readout circuitry and 14b high-speed redundant successive approximation register (SAR) ADCs [5] are adopted. As a result, a full-size image with a data rate of 128.71Gb/s at 60fps has been captured. Figure 6.2.1 shows the sensor block diagram. The total pixel array size is 15488(H) × 8776(V) including optical black pixels. The pixel design is a 2.45μm two-way vertically shared pinned photodiode. The readout of the array is addressed one physical pixel row at a time with 15,488 readout columns split between the top and bottom of the pixel array. The column readout circuit consists of a source-follower bias current (VLN), a programmable-gain amplifier (PGA), and two sets of sample-and-hold capacitor banks (SHCaps) for even-and-odd-row ping-pong operation. Analog data stored in the SHCaps are read out in parallel by 484 SAR-ADCs. Each SAR-ADC serially multiplexes 32 columns, and the resulting converter data are written into the SRAM line memory. Two banks of SRAM memory are used to provide pipelining of the ADC and SRAM readout to reduce the row time. The SRAM readout is further divided into 16 parallel ports to reduce the data rate. Each readout port outputs 960 columns, with the exception of the 4 edge corner ports that output an additional 32 optical black columns. CML output drivers are used to output 7b-wide data to a 574.56MHz DDR, achieving an aggregate data rate of 128.71Gb/s. The sensor block diagram is completed with distributed PLLs, SPI communication, and on-chip timing control logic. Figure 6.2.2 shows a simplified block diagram of the signal readout path and timing control logic blocks. The PGA, SHCaps, CMR, and ADC are similar to those described in [5], which enables us to design a large-format sensor at 60fps that fits into a 1D stitching reticle. Front-end multiplexing of the columns is optimized for 32 columns per CMR and a 14b SAR-ADC with a conversion r...

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We have developed a compact integral three-dimensional (3D) imaging equipment that positions the lens array and image sensor in close proximity to each other. In the conventional scheme, a camera lens is used to project the elemental images generated by the lens array onto the image sensor. In contrast, the imaging equipment presented here combines the lens array and image sensor into one unit and makes no use of a camera lens. This scheme eliminates the resolution deterioration and distortion caused by the use of a camera lens and improves, in principle, the quality of the reconstructed 3D image. We captured objects with this imaging equipment and displayed the reconstructed 3D images using display equipment consisting of a liquid crystal panel and a lens array. The reconstructed 3D images were found to have appropriate motion parallax.

This article describes an improvement in the noise reduction performance of a column correlated multiple sampling (CMS) readout circuit using interleaved pixel source follower for high-resolution and high-framerate CMOS image sensors (CISs). In this architecture, the timeinterleaved operation of the two pixel source followers reduces the restrictions imposed by the settling time of the pixel source followers and extends the time for multiple sampling. The noise analysis indicates that this method has an advantage of enhanced noise reduction not only for thermal noise but also for 1/f noise when a high-speed readout operation is required. The measurement of the noise performance of the 8K image sensor using the CMS with the interleaved pixel source follower method exhibits a low input-referred noise of 3.2 e − at 8K 120 frames per second, while 4.6 e − with the conventional single-source follower readout method. The measurement results match reasonably well with the analysis presented in this article, demonstrating the effectiveness of the interleaved pixel source follower method for high-resolution and high-framerate CISs.Index Terms-8K, CMOS image sensor (CIS), correlated multiple sampling (CMS), high resolution, noise reduction. I. INTRODUCTIONT HE recent trends in video applications have tended toward increasing spatial resolutions, such as 4K, 8K, and high framerates. The video parameters of an ultrahighdefinition television (UHDTV) are standardized in recommendations ITU-R BT.

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