This paper presents and discusses a Low-Band (LB) Low Noise Amplifier (LNA) design for a diversity receive module where the application is for multi-mode cellular handsets. The LB LNA covers the frequency range between 617 MHz to 960 MHz in 5 different frequency bands and a 5 Pole Single Throw (5PST) switch selects the different frequency bands where two of them are for the main and three for the auxiliary bands. The presented structure covers the gain modes from −12 to 18 dB with 6 dB gain steps where each gain mode has a different current consumption. In order to achieve the Noise Figure (NF) specifications in high gain modes, we have adopted a cascode Common-Source (CS) with inductive source degeneration structure for this design. To achieve the S11 parameters and current consumption specifications, the core and cascode transistors for high gain modes (18 dB, 12 dB, and 6 dB) and low gain modes (0 dB, −6 dB, and −12 dB) have been separated. Nevertheless, to keep the area low and keep the phase discontinuity within ±10∘, we have shared the degeneration and load inductors between two cores. To compensate the performance for Process, Voltage, and Temperature (PVT) variations, the structure applies a Low Drop-Out (LDO) regulator and a corner case voltage compensator. The design has been proceeded in a 65-nm RSB process design kit and the supply voltage is 1 V. For 18 dB and −12 dB gain modes as two examples, the NF, current consumption, and Input Third Order Intercept Point (IIP3) values are 1.2 dB and 16 dB, 10.8 mA and 1.2 mA, and −6 dBm and 8 dBm, respectively.

This paper presents a multi-gain radio frequency (RF) front-end low noise amplifier (LNA) utilizing a multi-core based on the source degeneration topology. The LNA can cover a wide range of input and output frequency matching by using a receiver (RX) switch at the input and a capacitor bank at the output of the LNA. In the proposed architecture here, to avoid the saturation of RX chain, 12 gain steps including positive, 0 dB, and negative power gains are controlled by a mobile industry processor interface (MIPI). The multi-core architecture offers the ability to control the power consumption over different gain steps. In order to avoid the phase discontinuity, the negative gain steps are provided using an active amplification and T-type attenuation path that keeps the phase discontinuity below ±5 degrees between two adjacent power gain steps. Using the multi-core structure, the power consumption is optimized in different power gains. The structure is enhanced with the adaptive variable cores and reactance parameters to maintain different power consumption for different gain steps and remain the output matching in an acceptable operating range. Furthermore, auxiliary linearization circuitries are added to improve the input third intercept point (IIP3) performance of the LNA. The chip is fabricated in 65 nm complementary metal-oxide semiconductor (CMOS) silicon on insulator (SOI) process and the die area is 0.308 mm2. The proposed architecture achieves the IIP3 performance of −10.2 dBm and 8.6 dBm in the highest and lowest power gains, which are 20.5 dB and −11 dB, respectively. It offers the noise figure (NF) performance of 1.15 dB in the highest power gain while it reaches 14 dB when the power gain is −11 dB. The LNA consumes 16.8 mA and 1.33 mA current from a 1 V power supply that is provided by an on-chip low-dropout (LDO) when it operates at the highest and lowest gains, respectively.

This paper presents a 2.15 µW/MHz at the frequency of 64 MHz relaxation oscillator with a dynamic range of frequency from 47.5 MHz to 80 MHz. To reduce the power consumption and improve energy efficiency, this work employs only one comparator and one capacitor to generate the output clock in comparison with conventional relaxation oscillator structures. A total of 50% ± 5% of the duty cycle is obtained for the output clock by implementing an auxiliary comparator. The proposed relaxation oscillator uses the output voltages of an external low-dropout (LDO) voltage and bandgap reference (BGR) for the required supply and reference voltages, respectively. Two current sources are implemented to provide the required currents for trimming the output frequency and driving the comparators. Measurement results indicate that the relaxation oscillator achieves a temperature coefficient (TC) of 130 ppm/°C over a wide temperature range from −25 °C to 135 °C at the frequency of 64 MHz. The relaxation oscillator consumes 115 µA of current at the frequency of 64 MHz under a low-dropout (LDO) voltage of 1.2 V. The proposed relaxation oscillator is analyzed and fabricated in standard 90 nm complementary metal-oxide semiconductor (CMOS) process, and the die area is 130 µm × 90 µm.