Adiabatic logic families require a power-clock generator (PCG) for the recovery of the energy. In this paper a fourphase PCG for positive feedback adiabatic logic with only one external inductor is presented. Closed form results for optimized design are obtained from a simple analysis of the scheme. An error below 7% respect to simulations confirms the validity of the approach. Comparisons with conventional CMOS systems, functionally similar to the adiabatic ones, show two to four times energy reduction.