Single-inductor four-phase power-clock generator for positive-feedback adiabatic logic gates

Blotti, A.; Borghese, S.; Saletti, Roberto

doi:10.1109/icecs.2002.1046218

Cited by 7 publications

(2 citation statements)

References 13 publications

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“…The drawn power is returned to the source, during recovery phase. The circuit waits for the logic from the previous stage to be calculated in the waiting phase [29]. This section presents the design of low power logic gates such as OR/NOR, AND/NAND and XOR/XNOR using modified PFAL and DC-DB PFAL.…”

Section: Implementation Of Logic Gates Using Different Adiabatic Techniquesmentioning

confidence: 99%

Low power architecture of logic gates using adiabatic techniques

Sanadhya

Sharma

2022

IJEECS

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The growing significance of portable systems to limit power consumption in ultra-large-scale-integration chips of very high density, has recently led to rapid and inventive progresses in low-power design. The most effective technique is adiabatic logic circuit design in energy-efficient hardware. This paper presents two adiabatic approaches for the design of low power circuits, modified positive feedback adiabatic logic (modified PFAL) and the other is direct current diode based positive feedback adiabatic logic (DC-DB PFAL). Logic gates are the preliminary components in any digital circuit design. By improving the performance of basic gates, one can improvise the whole system performance. In this paper proposed circuit design of the low power architecture of OR/NOR, AND/NAND, and XOR/XNOR gates are presented using the said approaches and their results are analyzed for powerdissipation, delay, power-delay-product and rise time and compared with the other adiabatic techniques along with the conventional complementary metal oxide semiconductor (CMOS) designs reported in the literature. It has been found that the designs with DC-DB PFAL technique outperform with the percentage improvement of 65% for NOR gate and 7% for NAND gate and 34% for XNOR gate over the modified PFAL techniques at 10 MHz respectively.

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Section: Implementation Of Logic Gates Using Different Adiabatic Techniquesmentioning

confidence: 99%

Low power architecture of logic gates using adiabatic techniques

Sanadhya

Sharma

2022

IJEECS

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“…Other than scaling down the operating voltage, innovative low power techniques such as adiabatic circuits have been seen in many recent publications. Adiabatic circuits achieve low energy consumption by using slowly increasing and than decreasing supply voltage [1], which sometimes can be approximated as an AC-type supply voltage [2], to recycle the energy stored on the load capacitances. Other than the characteristics of minimum operating voltage and maximum operating frequency, each style of adiabatic circuits requires a certain number of power clocks and constant supply voltages.…”

Section: Introductionmentioning

confidence: 99%

A novel fast low voltage dynamic threshold true single phase clocking adiabatic circuit

Yang

Barby

2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)

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A novel fast true single phase clocking (TSPC) adiabatic differential logic circuit using dynamic threshold (DTMOS) is proposed (DT-TSPC-A). It is capable of operating at 0.7V. The performance of four circuit architectures (DT-TSPC-A, conventional static CMOS logic, and two other published adiabatic circuits) is compared using a four inverter chain as the test circuit. At 50MHz and 0.8V with 20fF load, this circuit consumes the least amount of energy of the four circuit architectures compared. It takes about the same area and consumes 55% less energy than the static circuit. It has the shortest delay and is 56% faster than other adiabatic circuits and takes at most 2.3 times the area. In addition results for more complex circuits are supplied demonstrating the improved performance of DT-TSPC-A circuits.

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Generation of the Power-Clock

Teichmann

2012

Adiabatic Logic

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Single-inductor four-phase power-clock generator for positive-feedback adiabatic logic gates

Cited by 7 publications

References 13 publications

Low power architecture of logic gates using adiabatic techniques

Low power architecture of logic gates using adiabatic techniques

A novel fast low voltage dynamic threshold true single phase clocking adiabatic circuit

Generation of the Power-Clock

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