Experimental results on the high-voltage level shifter and dV=dt robustness of 1200 V high voltage integrated circuits (HVICs) using a self-isolation (SI) structure are reported for the first time. Generally, because high dV=dt stress is applied to HVICs during insulated gate bipolar transistor (IGBT) switching, significant displacement current flows through a highvoltage isolation capacitance. This current acts as the base current of parasitic pnp and npn transistors, and causes a potential drop in their base region. In the worst case, this parasitic operation causes device destruction. In this study, not only the normal operation of HVICs but suppression of the parasitic transistors under high dV=dt condition are experimentally demonstrated by considering a high-side layout design and back diverter electrode.

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