Experimental and Numerical Studies on dV/dt Robustness of 1200 V High-Voltage Integrated Circuits Using Self-Isolation Structure

Abstract

Experimental results on the high-voltage level shifter and dV=dt robustness of 1200 V high voltage integrated circuits (HVICs) using a self-isolation (SI) structure are reported for the first time. Generally, because high dV=dt stress is applied to HVICs during insulated gate bipolar transistor (IGBT) switching, significant displacement current flows through a highvoltage isolation capacitance. This current acts as the base current of parasitic pnp and npn transistors, and causes a potential drop in their base region. In the worst case, this parasitic operation causes device destruction. In this study, not only the normal operation of HVICs but suppression of the parasitic transistors under high dV=dt condition are experimentally demonstrated by considering a high-side layout design and back diverter electrode.

Proposal of a new lateral high-voltage n-channel MOS structure with a reduced parasitic output capacitance for a level-shift circuit integrated in 800 V-class high-voltage ICs

“…Our proposed device structure has been designed using the high-voltage isolation process based on a self-isolation technique. [1][2][3][4][5] The self-isolation technique is more cost effective than the junction isolation [8][9][10][11][12][13][14][15][16][17][18][19][20][21][22] and dielectric isolation techniques. [23][24][25][26][27][28][29][30] This is because it uses a lessexpensive silicon wafer that is uniformly doped, and it does not need special process steps such as deep diffusion layer and trench formations for the isolation process.…”

“…High-voltage ICs (HVICs) for driving the gates of power devices arranged in a bridge circuit configuration are intended for use in the development of power supply systems. [1][2][3][4][5] This is because the energy savings in power supply systems can be achieved by using the HVICs. One of the most important parameters of the HVICs to achieve the energy savings is the input=output (I=O) propagation delay time, which dominates the driving performance characteristics of low-side and highside power devices in a bridge circuit.…”

A 600 V High-Voltage IC Technique With a New Self-Shielding Structure for High Noise Tolerance and Die Shrink

“…Manuscript Reducing the chip size and applying the simplified process flow are also needed. The cross-sectional views of high-side isolation structure in conventional self-isolation (SI) [7], [8], junctionisolation (JI) [9]- [13], and dielectric-isolation (DI) [14]- [20] techniques are shown in Fig. 1(a)-(c), respectively.…”

Robustness of Self-Isolation High-Voltage Integrated Circuits against the Voltage Surge during Conductivity Modulation Delay in Free-Wheeling Diode

“…HVICs include both high-side and low-side gate drive circuits monolithically, and various isolation structures of these have been introduced and demonstrated. [1][2][3][4][5][6][7][8][9][10] A self-isolation structure is simple and cost-effective compared with other isolation structures, although a suppression of the parasitic transistor action should be considered. In this study, the robustness of selfisolation 1200 V HVICs against the surge during conductivity modulation delay in a FWD is examined experimentally by reducing parasitic bipolar transistor gain and optimizing sheet resistance from the viewpoint of reduced surface electric field (RESURF) and is reported here for the first time.…”