There is an urgent requirement for an optical emitter that is compatible with standard, silicon-based ultra-large-scale integration (ULSI) technology. Bulk silicon has an indirect energy bandgap and is therefore highly inefficient as a light source, necessitating the use of other materials for the optical emitters. However, the introduction of these materials is usually incompatible with the strict processing requirements of existing ULSI technologies. Moreover, as the length scale of the devices decreases, electrons will spend increasingly more of their time in the connections between components; this interconnectivity problem could restrict further increases in computer chip processing power and speed in as little as five years. Many efforts have therefore been directed, with varying degrees of success, to engineering silicon-based materials that are efficient light emitters. Here, we describe the fabrication, using standard silicon processing techniques, of a silicon light-emitting diode (LED) that operates efficiently at room temperature. Boron is implanted into silicon both as a dopant to form a p-n junction, as well as a means of introducing dislocation loops. The dislocation loops introduce a local strain field, which modifies the band structure and provides spatial confinement of the charge carriers. It is this spatial confinement which allows room-temperature electroluminescence at the band-edge. This device strategy is highly compatible with ULSI technology, as boron ion implantation is already used as a standard method for the fabrication of silicon devices.

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Document VersionPublisher's PDF, also known as Version of Record (includes final page, issue and volume numbers)Please check the document version of this publication:• A submitted manuscript is the author's version of the article upon submission and before peer-review. There can be important differences between the submitted version and the official published version of record. People interested in the research are advised to contact the author for the final version of the publication, or visit the DOI to the publisher's website.• The final author version and the galley proof are versions of the publication after peer review.• The final published version features the final layout of the paper including the volume, issue and page numbers. Link to publication Citation for published version (APA):Bergveld, H. J., Nowak, K., Karadi, R., Iochem, S., Ferreira, J., Ledain, S., ... Pommier, M. (2009). A 65-nm-CMOS 100-MHz 87%-efficient DC-DC down converter based on dual-die system-in-package integration. In Proc. IEEE Energy Conversion Congress and Exposition (ECCE'09), San Jose, USA, 20-24 Sept. 2009 (pp. 3698-3705 General rights Copyright and moral rights for the publications made accessible in the public portal are retained by the authors and/or other copyright owners and it is a condition of accessing publications that users recognise and abide by the legal requirements associated with these rights.• Users may download and print one copy of any publication from the public portal for the purpose of private study or research.• You may not further distribute the material or use it for any profit-making activity or commercial gain • You may freely distribute the URL identifying the publication in the public portal ? Take down policyIf you believe that this document breaches copyright please contact us providing details, and we will remove access to the work immediately and investigate your claim. Abstract --The increasing number of efficient voltage conversions realized in small volumes in many applications has introduced a trend towards small-form-factor DC-DC converters with integrated passives. Preferably, the DC-DC converter is integrated with the load, often in nm-CMOS, allowing for local supply optimization yielding increased power efficiency. However, energy-storage densities in nm-CMOS are low and silicon area is expensive. Therefore, to limit cost of monolithically integrated systems, passive components have low values, leading to very high switching frequencies, which compromises efficiency. This paper follows an alternative approach, where the active converter part is realized in 65-nm CMOS and the passive part in a low-cost high-density passiveintegration process. With the active die flip-chipped on the passive die a small System-in-Package (SiP) is obtained with a peak efficiency of 87.5% at 100 MHz switching frequency and 85 mW output power. This performance is mainly caused by the high quality of the integrated passives.

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