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BACKGROUND: Chronic pain conditions such as low back pain, knee pain and cervical pain are highly prevalent among female teachers. Chronic pain significantly affects the mental health, sleep and quality of life among teachers. OBJECTIVE: This study intended to investigate the impact of a workplace yoga intervention on musculoskeletal pain, anxiety, depression, sleep, and quality of life (QoL) among female teachers who had chronic musculoskeletal pain. METHOD: Fifty female teachers aged between 25–55 years with chronic musculoskeletal pain were randomized to either the yoga group (n = 25) or the control group (n = 25). The yoga group received a 60-minute structured Integrated Yoga intervention (IY) four days a week for six consecutive weeks at school. The control group received no intervention. Outcome measures: Pain intensity, anxiety, depression, stress, fatigue, self-compassion, sleep quality, and quality of life were assessed at the baseline and six weeks. RESULTS: A significant (p < 0.05) reduction in pain intensity and pain disability in the yoga group was observed after 6-week compared to baseline. Anxiety, depression, stress, sleep scores and fatigues also improved in the yoga group after six weeks. The control group showed no change. Post score comparison showed a significant difference between the groups for all the measures. CONCLUSION: Workplace yoga intervention is found to be effective in improving pain, pain disability, mental health, sleep quality among female teachers with chronic musculoskeletal pain. This study strongly recommends yoga for the prevention of work-related health issues and for the promotion of wellbeing among teachers.

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Modular Multiplication operations are widely used in Digital crypto processors. Modulo multipliers is an essential block for Residue Number System (RNS) computation. Pointing to increase the performance of the RNS computation, the parallel unsigned modulo multiplier for 2n-1 moduli is designed. A mathematical modelling, VLSI architecture and real-time verification are done in this work. Further, the modulo multipliers are described usingVerilog HDL, and the synthesize results for both FPGA and ASIC technologies are presented. Comparison is made based on the parameters such as Area, Power, Delay, PDP& ADP using Cadence RTL Compiler with 180 nm, 90 nm and 45 nm TSMC CMOS Technologies.From the analysis indicate that the proposed multiplier provides a 16% area reduction and 40% speed improvement with a better PDP and ADP performance compared tothe existing modulo multipliers. Finally, the usefulness of 2n-1 modulo multiplier in RNS environment is discussed.