Jefferson Lab's Continuous Electron Beam Accelerator Facility (CEBAF) uses Trim Card I power supplies to drive approximately 1900 correction magnets. These trim cards have had a long and illustrious service record. However, some of the employed technology is now obsolete, making it difficult to maintain the system and retain adequate spares. The Trim Card II is being developed to act as a transparent replacement for its aging predecessor. A modular approach has been taken in its development to facilitate the substitution of sections for future improvements and maintenance. The resulting design has been divided into a motherboard and 7 daughter cards which has also allowed for parallel development.The Trim Card II utilizes modern technologies such as a Field Programmable Gate Array (FPGA) and a microprocessor to embed trim card controls and diagnostics. These reprogrammable devices also provide the versatility to incorporate future requirements.

Modular Multiplication operations are widely used in Digital crypto processors. Modulo multipliers is an essential block for Residue Number System (RNS) computation. Pointing to increase the performance of the RNS computation, the parallel unsigned modulo multiplier for 2n-1 moduli is designed. A mathematical modelling, VLSI architecture and real-time verification are done in this work. Further, the modulo multipliers are described usingVerilog HDL, and the synthesize results for both FPGA and ASIC technologies are presented. Comparison is made based on the parameters such as Area, Power, Delay, PDP& ADP using Cadence RTL Compiler with 180 nm, 90 nm and 45 nm TSMC CMOS Technologies.From the analysis indicate that the proposed multiplier provides a 16% area reduction and 40% speed improvement with a better PDP and ADP performance compared tothe existing modulo multipliers. Finally, the usefulness of 2n-1 modulo multiplier in RNS environment is discussed.

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In this paper a method to build a faster array multiplier based on Radix 4 Modified Booth Encoder -which is broadly used for the signed multiplication applications-with less area and power is presented. This is achieved by optimizing the overall interconnection delay in the partial product array and by scheming the most efficient Full Adder and Booth Encoder in Complementary Pass Transistor Logic approach. The proposed array multiplier's performance in terms of delay, power and area is compared with conventional as well as Baugh-Wooley Multiplier. In order to optimize the power and area of the multiplier, a CPL Based MBE with standard partial product array is proposed and designed in full custom style. The use of efficient 10 Transistor based Full adders based on CPL logic ensures that the entire design is in CPL logic, which provides a regular outline with less interconnection intricacy.

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