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This paper compares the application of different constitutive material and fatigue models for lead-free (SnAg4.0CuO.5) solder proposed by Schubert, Wiese, Dudek and Syed. The application of these models is demonstrated and results are compared with the experimental findings for different type of Ball Grid Array packages, which are subjected to a controlled temperature cycling condition. In addition, a semi-empirical approach was used to fit the finite element modeling results with experimental temperature cycling test data for 2nd level solder joint fatigue failures.

We report board level stress tests of leadless QFN packages (pitch 0.5 mm) with focus on different application fields. We did temperature cycling tests, drop test, bend test, and power cycling tests, with special focus on the influences of board design and soldering technology. We performed the stress tests until end-of-life and determined the dominating failure modes. In our temperature cycling study on 2.35 mm thick boards solder joints of SnAgCu performed slightly worse than SnPbAg. We were able to optimize the thermal pad design on the PCB to improve the temperature cycling reliability. For drop test we achieved an excellent reliability by comparing different board designs. This was achieved by avoiding copper trace cracking within the board. This failure mode we verified also with cyclic bend tests. Additionally we performed power cycling investigations using different power consumptions and solder pastes for board assembly (SnAgCu and SnPbAg). A strong lifetime dependence on power and a superior behavior of SnAgCu solder was found. The results were successfully correlated with finite element simulations. In our stress tests we observed clear evidence for influence of soldering technology and board design/technology on board level reliability performance. For different application fields satisfactory reliability can be achieved in case specific measures on board assembly and printed circuit board design are taken. IntroductionDuring the last years Quad Flat No-lead (QFN) packages became very popular as cost effective solution for low pincount IC products. A QFN is a plastic encapsulated package with a copper leadframe, which is exposed on the package bottom side. The peripheral leads as well as the exposed die pad can be soldered to the printed circuit board (PCB) by standard SMT processes. Figure 1 shows a schematic cross section of a QFN on a PCB.