We propose HfSi x /HfO 2 gate stacks as the most suitable combination for high performance nMOSFETs.An equivalent work function (WF) to n + poly-Si was obtained by controlling Hf/Si ratio of the electrode. The highest electron mobility ever reported was achieved in the thinner Tinv region down to 1.6nm by low temperature process without using plasma nitridation both for metal and high-k fabrication. As a result, the extremely high drive current of 1.25mA/um at off-state leakage of 1nA/um and low gate leakage current of 0.3A/cm 2 were obtained at Vdd=1.3V with 65nm gate length nMOSFETs without strain enhanced technology.

In order to achieve high throughput Cu-CMP compatible with low step heights in 32nm Node copper interconnect technologies and beyond, we believe it is crucial a passivation layer on the Cu surface in the slurry during the CMP process. We show that the formation of a passivation layer which achieves good planarization with high Cu removal rate can be controlled by selecting the rest potential of the Cu ions in the slurry.

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