Abstract. Advances in VLSI technology have lead to a tremendous increase in the density and number of devices that can be manufactured in a single microchip. One of the interesting ways in which this silicon may be used is to leave portions of it uncommitted and re-programmable depending on an applications needs. In an earlier paper, we proposed a machine architecture for achieving this reconfigurability and compilation issues that such an architecture will face. In this paper, we will elaborate on the compiler optimization issues involved. In particular, we will outline a framework for code partitioning, instruction synthesis, configuration selection, resource allocation, and instruction scheduling. Partitioning is the problem of identifying code sections that may benefit by mapping them on to the programmable logic resources. The instruction synthesis phase generates suitable implementations for the candidates partitions and updates the machine description database with the new instructions. Configuration selection is the problem of narrowing down the choices of which synthesized instruction (from the set generated by the instruction synthesis phase) to use for each of the code regions that will be mapped to programmable logic. Unlike traditional optimizing compilers, the adaptive EPIC compiler must deal with the existence of synthesized instructions. Compilation techniques addressing each of these problems will be presented.

No abstract

W e propose a novel approach to harness the idle cycles of workstations connected by L A N / W A N s for long running scientific computations and present performance results for our prototype system called Persistent Linda (PLinda). PLinda offers low runtime overhead and, migration among heterogeneous architectures while retreating quickly when owners return to their workstations. PLinda achieves this by implementing a lightweight transaction model that lacks serializability and durability, but preserves a basic guarantee: if a PLinda execution terminates, it has the same result as some failure-free Linda execution. Further, by storing the state of a PLinda process as a set of core variables as of each transaction commit, a PLinda process can migrate among different architectures.Within the space of lightweight transaction models, we offer three mechanisms that make different tradeoffs between failure-free performance and recovery time. All three mechanisms may be used at the same time in a single application; each process using the mechanism which is best suited for its characteristics. Our experiments illustrate the tradeoffs of the three mechanisms as well as the overall performance of the system on applications from physics and finance.

Recoi,/giirublc r.o,nprrting ofers the embedded systems designem the flexibility of application specrflc opti,nixitioiis 011 (I genrricplnrjbrm. In thispoper, we are rwremrd with U ./ine-gmbi. tight(v coupled, dynamically r.er.o,lfiguroble ai-chitect~rre we call Adaptive EPIC. A g o m i c EPIC airhirectrrre is augmented wirh a ~~~m i c a l l y reconjiS.ro.able sfructuie. In this paper, vve describe (or aperirrzental setup IO evaluate the pvfomafrc~' of'rnch a processor. Our results show that suclr architrct~rre can ofer signijicont performance irnprovements fix-low freyirency, and hence low power, cure "r"cesS0Is.