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Cryptography is a technique related to aspects of information security such as data confidentiality, data integrity and entity authentication. In data and telecommunication systems, Security is the most important part for an effective communication, where to increase the security as well as complexity, more randomization in secret keys is necessary to enhance the cryptography algorithms. In traditional AES, Even though the round keys have high security, Power analysis attack and Saturation attack are effective to the key expansion algorithm of AES due to the deducible key rounds and it leads to security problems. As a result, a new algorithm for generation of round keys is developed for AES. On hardware platform, these algorithms are realizing with enormous memory spaces and large execution time. An alternative hardware platform scenario is provided by Field programmable gate arrays (FPGAs) due to its reconfiguration nature, marketing speed and low price. Accordingly, a hardware implementation of the AES-128 encryption and decryption algorithm with the new algorithm of round key expansion is proposed to improve the security against such attacks. This structure will experimentally simulate using Xilinx software with Verilog HDL and hardware implementation on FPGA.

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Industries attention is lots more on Elliptic Curve Cryptography (ECC). ECC offers equal security for smaller bit size than RSA where larger key size is required, which reduces the processing complexity. Encryption and Decryption methods of ECC will not work on messages but is on curve performance. In this paper fast mapping method based on a matrix approach for ECC is studied, where high security for the encrypted message is offered. Initially, the alphabets present in the message is mapped to the points present on an elliptic curve. Later those points are encoded using ElGamal encryption method by using a non-singular matrix. The original message is obtained by decrypting the encoded message using ElGamal decryption technique, the decoded matrix is multiplied with the inverse of non-singular matrix. The Verilog Code is used. FPGA simulate and synthesize the proposed design