Objective of multivalve logic design is to reduce number of gates needed and also to reduce interconnect path length. Interconnect path consist of the largest number of gates from input to output. The reason of these two objectives is that they will give extremely good properties when implemented in VLSI. Reducing number of gates will reduce the chip area, and minimizing interconnect path length will give opportunity to use highest clock frequency. In this paper quaternary to binary and binary to quaternary converter are designed. We can design the multivalve logic to binary converter which is use for conversion of ternary-valued input 0,1,2 and quaternaryvalued input 0,1,2,3 into corresponding binary-valued output 0,1. The physical design of the circuits is simulated and tested with MICROWIND layout design tool in 50nm technology. The conversion method is simple and compatible with the present CMOS process. The circuits could be embedded in digital CMOS VLSI design architectures.

The popularity and necessity of portable electronic systems by users have strongly influenced VLSI designers to make great effort for reduced silicon area, improved speeds, long duration battery life, and great reliability. The VLSI designers always try to save power consumption while designing a system. In this paer, an efficient methodology is presented to improve the output swing level of GDI gates. New designs of GDI based basic digital (AND, OR, XOR, XNOR) gates are presented using single pass transistors to improve swing level of GDI gates. The new design of basic gates with combination of GDI logic and pass transistor logic is called hybrid GDI technique. Compared to existing GDI technique with buffer restoration circuits, hybrid GDI implementation provides full swing output voltage in all digital circuits. Also it shows less power and less delay with about 60% area increase as compared to basic GDI.

Abstract-Synchronizers were required when reading an asynchronous input. In a multi clock system, synchronizers are required when on-chip data cross the clock domain boundaries which guard against synchronization failures but introduce latency in processing the asynchronous input. We use method that hides synchronization latency by overlapping it with computation cycles Synchronous logic is designed such that state bit transitions have sufficient time to propagate to subsequent flip-flops by the time of the following clock edge. If one flip-flop k becomes metastable and produces a transition whose clock-to-q delay is longer than expected, this transition may not have sufficient time to reach all destination flip-flops.

The synchronizer is constrained such that its state does not change when a latching operation fails. Therefore, any failed latching attempts are automatically retried in the subsequent cycles. For this we simulates the 8 bit multiplier, 4 bit 16 state finite state machine, 16 slot 8 bit data first in first out register etc. In a multi clock system, synchronizers are required when on-chip data cross the clock domain boundaries which guard against synchronization failures but introduce latency in processing the asynchronous input. We use method that hides synchronization latency by overlapping it with computation cycles Synchronous logic is designed such that state bit transitions have sufficient time to propagate to subsequent flip-flops by the time of the following clock edge. If one flip-flop k becomes metastable and produces a transition whose clock-to-q delays is longer than expected, this transition may not have sufficient time to reach all destination flip-flops.

No abstract