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Glial cells, also known as neuroglia or glia, are non-neuronal cells providing support and protection for neurons in the central nervous system (CNS). They also act as supportive cells in the brain. Among a variety of glial cells, the star-shaped glial cells, i.e., astrocytes, are the largest cell population in the brain. The important role of astrocyte such as neuronal synchronization, synaptic information regulation, feedback to neural activity and extracellular regulation make the astrocytes play a vital role in brain disease. This paper presents a modified complete neuron-astrocyte interaction model that is more suitable for efficient and large scale biological neural network realization on digital platforms. Simulation results show that the modified complete interaction model can reproduce biological-like behavior of the original neuron-astrocyte mechanism. The modified interaction model is investigated in terms of digital realization feasibility and cost targeting a low cost hardware implementation. Networking behavior of this interaction is investigated and compared between two cases: i) the neuron spiking mechanism without astrocyte effects, and ii) the effect of astrocyte in regulating the neurons behavior and synaptic transmission via controlling the LTP and LTD processes. Hardware implementation on FPGA shows that the modified model mimics the main mechanism of neuron-astrocyte communication with higher performance and considerably lower hardware overhead cost compared with the original interaction model.

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Implementation of neural networks in case of hardware helps us to understand the different parts of the human brain operation, using artificial intelligence (AI). This paper presents a new model of the Hindmarsh-Rose (HR) Neuron that is based on basic polynomial functions called Nyquist-look up table-Hindmarsh-Rose (N-LUT-HR) based on an accurate sampling of the original model. The proposed approach is investigated in terms of its digital realization feasibility. According to high matching between the original and proposed terms, it is showed that the new modified model can follow all spiking patterns of primary model with low-error computations. In hardware case, the proposed and original models are implemented on Xilinx FPGA XC2VP30 chip to validate different aspects of the simulation results. Hardware results demonstrate that our model regenerates the desired patterns in low-cost and high-frequency (speed-up) in comparison with the other similar works. Overall saving in FPGA resources show that this new model is capable of being used in large-scale networks in case of minimum required resources (FPGA costs). In addition, the analysis of hardware indicates that the new circuits can work in a maximum frequency of 123 MHz with 98.25% saving in FPGA costs (resources utilization of FPGA).