The current trend to move from homogeneous to heterogeneous multicore systems provides compelling opportunities for achieving performance and energy efficiency goals. Running multiple threads in multicore systems poses challenges on meeting limited shared resources, such as memory bandwidth. We propose an optimization approach that includes an Integer Linear Programming (ILP) optimization model and a scheme to dynamically determine thread-to-core assignment. We present simulation analysis that shows energy savings and performance gains for a variety of workloads compared to state-of-the-art schemes. We implemented and evaluated a prototype of our thread assignment approach at user level, leveraging Linux scheduling and performance-monitoring capabilities.

TDMA has been proposed as a MAC protocol for wireless sensor networks (WSNs) due to its efficiency in high WSN load. However, TDMA is plagued with shortcomings; we present modifications to TDMA that will allow for the same efficiency of TDMA, while allowing the network to conserve energy during times of low load (when there is no activity being detected). Recognizing that aggregation plays an essential role in WSNs, TDMA-ASAP adds to TDMA: (a) transmission parallelism based on a level-by-level localized graph-coloring, (b) appropriate sleeping between transmissions ("napping"), (c) judicious and controlled TDMA slot stealing to avoid empty slots to be unused and (d) intelligent scheduling/ordering transmissions. Our results show that TDMA-ASAP's unique combination of TDMA, slot-stealing, napping, and message aggregation significantly outperforms other hybrid WSN MAC algorithms and has a performance that is close to optimal in terms of energy consumption and overall delay.

In Wireless Sensor Networks (WSNs), the users' objective is to extract useful global information by collecting individual sensor readings. Conventionally, this is done using in-network aggregation on a spanning tree from sensors to data sink. However, the spanning tree structure is not robust against communication errors; when a packet is lost, so is a complete subtree of values. Multipath routing can mask some of these errors, but on the other hand, may aggregate individual sensor values multiple times. This may produce erroneous results when dealing with duplicate-sensitive aggregates, such as SUM, COUNT, and AVERAGE. In this paper, we present and analyze two new fault tolerant schemes for duplicate-sensitive aggregation in WSNs: (1) Cascaded RideSharing and (2) Diffused RideSharing. These schemes use the available path redundancy in the WSN to deliver a correct aggregate result to the data sink. Compared to state-of-the-art, our schemes deliver results with lower root mean square (RMS) error and consume much less energy and bandwidth. RideSharing can consume as much as 50% less resources than hash-based schemes, such as SKETCHES and Synopsis Diffusion, while achieving lower RMS for reasonable link error rates.

Abstract-

Network function virtualization (NFV) promises significant cost savings, flexibility and ease of deployment. However, potential challenges in implementing virtualized network elements that can support real-world performance requirements are still an open question. For example, traditional telecom networks have a lot of complex interdependencies that can affect performance. In this paper, we study the potential bottlenecks in virtualizing cellular core network functions. Using a combination of analysis and experimentation, we quantify the impact of software-based EPC elements on various metrics including physical processing, memory, IO, and bandwidth resource requirements. We use production grade, software-based cellular network elements running on general purpose Linux servers, driven by a variety of realistic workloads derived from a realworld cellular network, to examine the combined effects of control and data planes on an LTE enhanced packet core (EPC). In particular, we discover that the SGW handles about 33% of the control plane transactions and is a potential source for performance bottlenecks as a result of the interdependencies between control and data plane processing. Our results indicate that simply replacing existing EPC elements with virtualized equivalents can have severe performance bottlenecks and that virtualized EPC elements need to be carefully designed.