We report a fabrication process of pixel detectors made of bulk cadmium telluride (CdTe) crystals. Prior to processing, the quality and defect density in CdTe material was characterized by infrared (IR) spectroscopy. The semiconductor detector and Flip-Chip (FC) interconnection processing was carried out in the clean room premises of Micronova Nanofabrication Centre in Espoo, Finland. The chip scale processes consist of the aluminum oxide (Al 2 O 3 ) low temperature thermal Atomic Layer Deposition (ALD), titanium tungsten (TiW) metal sputtering depositions and an electroless Nickel growth. CdTe crystals with the size of 10 × 10 × 0.5 mm 3 were patterned with several photo-lithography techniques. In this study, gold (Au) was chosen as the material for the wettable Under Bump Metalization (UBM) pads. Indium (In) based solder bumps were grown on PSI46dig read out chips (ROC) having 4160 pixels within an area of 1 cm 2 . CdTe sensor and ROC were hybridized using a low temperature flip-chip (FC) interconnection technique. The In-Au cold weld bonding connections were successfully connecting both elements. After the processing the detector packages were wire bonded into associated read out electronics. The pixel detectors were tested at the premises of Finnish Radiation Safety Authority (STUK). During the measurement campaign, the modules were tested by exposure to a 137 Cs source of 1.5 TBq for 8 minutes. We detected at the room temperature a photopeak at 662 keV with about 2 % energy resolution.

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We report on a continuous plasma etching process using SF 6 /O 2 /Ar gases for fabricating 100 μm deep tapered through-silicon vias (TSV). The mask diameters of the vias were 20, 30 and 50 μm. The flow rates of the process gases were changed to study their individual effect on the profile angle, via depth, sidewall roughness, and sideways undercut of the tapered vias. Tapered vias having profile angles varying from 70 • to 85 • and smooth sidewalls were etched by balancing the chemically-assisted isotropic etching of F * radicals, passivation film by O 2 , and ion-assisted passivation etching. Although, the profile angles of the etched vias were reduced by either increasing the SF 6 flow rate or by reducing the O 2 flow rate, the effect of SF 6 gas was found to be dominant. The flow rates of SF 6 and O 2 were found to be the important factors which determine the continuous tapering of the vias with smooth via sidewalls. Ar gas flow rate did not significantly affect the tapered silicon vias and the profile angle. After considering the individual effects of each gas, an optimized etching recipe was fixed, which was used to etch 100 μm deep vias having a profile angle of 83 • . Conformal layers of insulation and copper seed layers were deposited in the tapered vias. The tapered vias were partially filled by copper electrodeposition and redistribution lines were formed. The electrical resistance of tapered TSVs was measured to be between 3-8 m for the majority of the TSVs, making these TSVs suitable for various MEMS packaging applications.

This paper presents the fabrication and the electrical characterization of poly-Si filled through-silicon vias, which were etched in a 180 μm thin silicon device wafer, bonded to a handle wafer by plasma activated oxide-to-silicon bonding. Heavily doped poly-Si was used as interconnection material, which was deposited by low-pressure chemical vapor deposition. Two different via geometries, i.e. stadium shaped, and circular shaped, were tried. Sputtered aluminum metallization layers as double-side redistribution lines and contact pads, were used. Both Kelvin structures and daisy chains were fabricated and their electrical resistances were measured. The electrical resistance of a single stadium-shaped via was measured to be about 24 . The electrical resistance was varying from 60 to 90 for two-vias daisy chains. Measured results indicate that this via-first technology can be used for varying range of sensor applications like microphone, oscillator, resonator, etc where CMOS compatibility and high temperature processing are the prime requirements.