Oxide semiconductors typically show superior device performance compared to amorphous silicon or organic counterparts, especially when they are physical vapor deposited. However, it is not easy to reproduce identical device characteristics when the oxide field-effect transistors (FETs) are solution-processed/printed; the level of complexity further intensifies with the need to print the passive elements as well. Here, we developed a protocol for designing the most electronically compatible electrode/channel interface based on the judicious material selection. Exploiting this newly developed fabrication schemes, we are now able to demonstrate high-performance all-printed FETs and logic circuits using amorphous indium-gallium-zinc oxide (a-IGZO) semiconductor, indium tin oxide (ITO) as electrodes, and composite solid polymer electrolyte as the gate insulator. Interestingly, all-printed FETs demonstrate an optimal electrical performance in terms of threshold voltages and device mobility and may very well be compared with devices fabricated using sputtered ITO electrodes. This observation originates from the selection of electrode/channel materials from the same transparent semiconductor oxide family, resulting in the formation of In-Sn-Zn-O (ITZO)-based-diffused a-IGZO-ITO interface that controls doping density while ensuring high electrical performance. Compressive spectroscopic studies reveal that Sn doping-mediated excellent band alignment of IGZO with ITO electrodes is responsible for the excellent device performance observed. All-printed n-MOS-based logic circuits have also been demonstrated toward new-generation portable electronics.

2D semiconductors, such as transition metal dichalcogenides (TMDs) show a rare combination of physical properties that include a large‐enough bandgap to ensure sufficient current modulation in transistors, matching electron and hole mobility for complimentary logic operation, and sufficient mechanical flexibility of the nanosheets. Moreover, the solvent‐exfoliated TMD‐nanosheets may also be processed at low temperatures and onto a wide variety of substrates. However, the poor inter‐flake transport in solution‐cast 2D‐TMD network transistors hinders the realization of high device mobility and current modulations that the intraflake transistors can regularly demonstrate. In this regard, fully printed and electrolyte‐gated, narrow‐channel MoS2 field‐effect transistors (FETs) with simultaneous high current saturation (>310 µA µm−1) and on–off ratio (>106) are proposed here. The transport limitation is overcome by printing an additional metal layer onto the 2D‐TMD nanosheet channel, which substantially shortens the effective channel lengths and results in predominant intraflake transport. In addition, a channel‐capacitance‐modulation induced subthermionic transport is recorded, which leads to a subthreshold slope value as low as 7.5 mV dec−1. On the other hand, thermionic MOSFETs and fully printed depletion‐mode NMOS inverters are also presented. The demonstrated generic approach involving chemically exfoliated nanosheet inks and the absolute device yield indicates the feasibility of fully printed 2D‐TMD electronics.

Inkjet-printed co-continuous mesoporous structures have been demonstrated for a large set of functional oxides. Channel-length-independent electronic transport was achieved when the mesoporous oxides were used to obtain printed, vertical edge FETs.

Here, the first term, V GS S ψ ∂ ∂ , known as the "body factor", cannot be less than 1 for standard MOSFET electrostatics, and the second term log I ( ) S 10 D ψ ∂ ∂ that is equals ln(10) β K T q and is 60 mV dec −1 at room temperature, determines the minimum limit of the subthreshold swing for the thermionic emission over the Boltzmann barrier. This in turn defines the steepness/slope of the transfer curves, the signal gain and the dynamic power dissipation of the electronic switches. One way to circumvent this limit is to allow tunneling through the barrier; in this case band-to-band-tunneling (BTBT) would be required as single career tunneling cannot lead to subthermionic transport. [2] However, the BTBT field-effect transistors (FETs) typically show low Oncurrents; while there are large number of subthermionic tunnel FETs reported in the literature, [3][4][5][6][7][8][9][10][11][12][13] the recent ones based on 2D dichalcogenides demonstrate particularly high performance. [2,14,15] An alternative approach to achieve subthermionic transport, originally proposed by Salahuddin and Datta [16] and later experimentally demonstrated by various research groups, [16][17][18][19][20][21][22][23][24][25][26][27] deals with concept that can actually reduce the body factor to values less than 1. This involves stabilizing a negative capacitance regime by placing a ferroelectric and dielectric layer in series to comprise the MOS capacitor. In this case, the Boltzmann activation barrier remains intact; however, an artificial voltage amplifier or step-up transformer is created using the sharp switching of the dipoles (i.e., exploiting the square-shaped P-E loop) of the ferroelectric and thereby a faster change in Ψ S (surface potential) becomes possible, as compared to the applied ∂V GS . However, in either of these approaches, specific requirements in terms of semiconductors (e.g., single sheet of 2D material), dielectrics or interfaces (e.g., ferroelectric/dielectric interface in case of negative capacitance (NC)-gate FETs) are there, which are certainly nontrivial to be replicated, when the complete device is to be solution processed/printed. Consequently, subthermionic transport Subthreshold slope of field-effect transistors (FETs) less than the fundamental Boltzmann limit (60 mV dec −1 at 300 K) is demonstrated either using band-to-band tunneling or negative capacitance (NC) ferroelectric-gate transistors. However, it is difficult to replicate both of these strategies in solution-processed/printed FETs. Nonetheless, it is shown that the use of a metal-insulator-metal-semiconductor architecture alongside electrolyte gating can simultaneously create highly reproducible static negative capacitance behavior in printed FETs, resulting in subthermionic transport for over four decades of drain currents with a subthreshold slope as low as 16 mV dec −1 , and thereafter a strong thermionic transport regime, characterized by an unprecedented On-current of 195 µA µm −1 , a transconductance of 215 µS µm, and a metal-like On-state res...

Oxide semiconductors are becoming an increasingly attractive choice for solution processed/printed transistors and circuits, as they possess numerous critical advantages over the other printable semiconductor technologies, such as abundance, low‐cost, environmental/thermal stability, nontoxicity, and most importantly, excellent electronic transport properties. However, on the downside, there are also major challenges, one of which is their high process temperatures, especially when they are processed from oxide precursors. In order to address this limitation, here, a general recipe for low temperature curable nanodispersions/nanoinks is proposed using aromatic surfactants that sublimates near room temperature. In this regard, stable nanoinks from In2O3 nanoparticles, with high particle loading, are developed using an inexpensive, nontoxic aromatic compound thymol as the stabilizer; while, thymol sublimates near room temperature (<40 °C), a quick heating at 100 °C is carried out to ensure its complete removal. The printed field‐effect transistors from thymol‐stabilized nanoinks show an on/off ratio >107, a maximum device mobility of 13.5 cm2 V−1 s−1, and transconductance values as high as 10 µS µm−1. It is believed that this general route to obtain low temperature curable electronic grade nanodispersions may find applications beyond the printed logic electronics demonstrated in the present study.