We present high performance silicon photonic circuits (PICs) defined for off-chip or on-chip photonic interconnects, where PN depletion Mach-Zehnder modulators and evanescent-coupled waveguide Ge-on-Si photodetectors were monolithically integrated on an SOI wafer with CMOS-compatible process. The fabricated silicon PIC(off-chip) for off-chip optical interconnects showed operation up to 30 Gb/s. Under differential drive of low-voltage 1.2 V(pp), the integrated 1 mm-phase-shifter modulator in the PIC(off-chip) demonstrated an extinction ratio (ER) of 10.5dB for 12.5 Gb/s, an ER of 9.1dB for 20 Gb/s, and an ER of 7.2 dB for 30 Gb/s operation, without adoption of travelling-wave electrodes. The device showed the modulation efficiency of V(π)L(π) ~1.59 Vcm, and the phase-shifter loss of 3.2 dB/mm for maximum optical transmission. The Ge photodetector, which allows simpler integration process based on reduced pressure chemical vapor deposition exhibited operation over 30 Gb/s with a low dark current of 700 nA at -1V. The fabricated silicon PIC(intra-chip) for on-chip (intra-chip) photonic interconnects, where the monolithically integrated modulator and Ge photodetector were connected by a silicon waveguide on the same chip, showed on-chip data transmissions up to 20 Gb/s, indicating potential application in future silicon on-chip optical network. We also report the performance of the hybrid silicon electronic-photonic IC (EPIC), where a PIC(intra-chip) chip and 0.13μm CMOS interface IC chips were hybrid-integrated.

With the concept of minimal invasiveness, if the patient's DisXE exceeds 9 cm, the length of the minilaparotomy incision in laparoscopic surgery could be disadvantageous. Nevertheless, we consider LATG the treatment of choice for early gastric cancer. If the patient's DisXE exceeds 9 cm, we consider intracorporeal anastomosis with the laparoscopic total gastrectomy. The type of esophagojejunostomy may be determined preoperatively by using three-dimensional abdominal computed tomography.

We present high-sensitivity photoreceivers based on a vertical- illumination-type 100% Ge-on-Si p-i-n photodetectors (PDs), which operate up to 50 Gb/s with high responsivity. A butterfly-packaged photoreceiver using a Ge PD with 3-dB bandwidth (f(-3dB)) of 29 GHz demonstrates the sensitivities of -10.15 dBm for 40 Gb/s data rate and -9.47 dBm for 43 Gb/s data rate, at BER of 10(-12) and λ ~1550 nm. Also a photoreceiver based on a Ge PD with f(-3dB)~19 GHz shows -14.14 dBm sensitivity at 25 Gb/s operation. These results prove the high performance levels of vertical-illumination type Ge PDs ready for practical high-speed network applications.

This paper reports a fiber-to-chip coupler consisting of a silicon inverted taper and a silicon oxynitride (SiON) double stage taper, where the cascaded taper structure enables adiabatic mode transfer between a submicron silicon waveguide and a single mode fiber. The coupler, fabricated by a simplified process, demonstrates an average coupling loss of 3.6 and 4.2 dB for TM and TE polarizations, respectively, with a misalignment tolerance of ± 2.2 µm for 1 dB loss penalty.

When silicon photonic integrated circuits (PICs), defined for transmitting and receiving optical data, are successfully monolithic-integrated into major silicon electronic chips as chip-level optical I/Os (inputs/outputs), it will bring innovative changes in data computing and communications. Here, we propose new photonic integration scheme, a single-chip optical transceiver based on a monolithic-integrated vertical photonic I/O device set including light source on bulk-silicon. This scheme can solve the major issues which impede practical implementation of silicon-based chip-level optical interconnects. We demonstrated a prototype of a single-chip photonic transceiver with monolithic-integrated vertical-illumination type Ge-on-Si photodetectors and VCSELs-on-Si on the same bulk-silicon substrate operating up to 50 Gb/s and 20 Gb/s, respectively. The prototype realized 20 Gb/s low-power chip-level optical interconnects for λ ~ 850 nm between fabricated chips. This approach can have a significant impact on practical electronic-photonic integration in high performance computers (HPC), cpu-memory interface, hybrid memory cube, and LAN, SAN, data center and network applications.