The thermal gradients existing in high-performance circuits may significantly affect their timing behavior, in particular by increasing the skew of the clock net and/or altering hold/setup constraints, possibly causing the circuit to operate incorrectly. The knowledge of the spatial distribution of temperature can be used to properly design a clock network that is able to compensate such thermal non-uniformities.However, re-design of the clock network is effective only if temperature distribution is stationary, i.e., does not change over time. In this work, we specifically address the problem of dynamically modifying the clock tree in such a way that it can compensate for temporal variations of temperature. This is achieved by exploiting the buffers that are inserted during the clock network generation, by transforming them into tunable delay elements. Temperature-induced delay variations are then compensated by applying the proper tuning to the tunable buffers, which is computed off-line and stored in a tuning table inserted in the design. We propose an algorithm to minimize the number of inserted tunable buffers, as well as their tunable range (which directly relates to complexity). Results show that clock skew is kept within original bounds with minimum area and power penalty. The maximum increase in power is 23.2% with most benchmarks exhibiting less than 5% increase in power.

As technologies continue to shrink in size, modeling the effect of process variations on circuit performance is assuming profound significance. Process variations affect the onchip performance of both active and passive components. This necessitates the inclusion of the effect of these variations on distributed interconnect structures in modeling overall circuit performance. In this work, first it is shown through field-solver simulations that larger process variations lead to non-Gaussian PDFs (Probability Density Functions) for the circuit equivalent parameters of distributed passives. Next, a method for accurate statistical analysis of coupled circuit-EM (Electromagnetic) systems without computing the equivalent circuit parameters of EMmodeled objects is demonstrated. This method also obviates the need to generate random variables representing the equivalent circuit parameters, from distributions which are correlated, nonGaussian and non-closed-form. The proposed approach relies on application of the Response Surface (RS) methodology to the y-parameters of both the circuit and the distributed structures independently and expressing the eventual performance measures through a suitable combination of the y-parameters. The eventual performance measures are expressed through a hierarchical approach in terms of the underlying Gaussian random variables representing the process parameters. A rapid Response Surface Monte Carlo (RSMC) analysis on these derived response surfaces furnishes the PDFs and can also be used to predict the yield based on different qualifying criteria and objective functions.

Leakage power is a serious concern in nanometer CMOS technologies. In this paper we focus on leakage reduction through automatic insertion of sleep transistors for power gating in standard cell based designs. In particular, we propose clustering algorithms for rowbased power-gating methodology which is based on using rows of the layout as the granularity for clustering. Our clustering methodology does timing and area constraint driven power-gating in contrast to only timing driven power-gating as proposed in the previous works. We present two distinct clustering algorithms with different accuracy-efficiency trade-off. An optimal one, which exploits a 0-1 or Binary Integer Programming approach, and a heuristic one, which resorts to an implicit enumeration of the layout rows. Results show that, for all the benchmarks, the leakage power savings, as compared to previous techniques, are more than 75% when we have the same timing constraints but half sleep transistor area and at least 60% when area constraint is set at one fourth. We also show that we can perform clustering with no speed degradation and achieve maximum leakage power savings up-to 83%.