A Scalable Algorithmic Framework for Row-Based Power-Gating

Abstract

Leakage power is a serious concern in nanometer CMOS technologies. In this paper we focus on leakage reduction through automatic insertion of sleep transistors for power gating in standard cell based designs. In particular, we propose clustering algorithms for rowbased power-gating methodology which is based on using rows of the layout as the granularity for clustering. Our clustering methodology does timing and area constraint driven power-gating in contrast to only timing driven power-gating as proposed in the previous works. We present two distinct clustering algorithms with different accuracy-efficiency trade-off. An optimal one, which exploits a 0-1 or Binary Integer Programming approach, and a heuristic one, which resorts to an implicit enumeration of the layout rows. Results show that, for all the benchmarks, the leakage power savings, as compared to previous techniques, are more than 75% when we have the same timing constraints but half sleep transistor area and at least 60% when area constraint is set at one fourth. We also show that we can perform clustering with no speed degradation and achieve maximum leakage power savings up-to 83%.

Low Power Reduction Techniques Implementation and Analysis in Sense Amplifier Circuit Configurations

“…Any of the division transistors can be coupled with a single sleep transistor. When a device is shut off, a sleep transistor breaks the device's connection to the earth and the network's power supply [7]. The device then runs out of power.…”

Using Power Reduction Techniques, a Comparison of Differential and Latch Type Sense Amplifier Circuits

“…The sensing amplifier is a crucial element in terms of memory. Sense amplifiers (SAs) have developed into a distinct class of semiconductor memory circuits due to their quick evolution [23][24][25][26][27]. Since sensing does not damage the circuits, it is not necessary to feed the circuits with new data after sensing.…”

“…Cache memory information can take up as much as sixty to seventy percent of the chip"s surface area. When additional chips are used, the speed of the CPU slows down [6][7][8]. Businesses are looking at the possibility of developing a low-speed, low-power memory circuit to keep up with the ever-increasing expansion of VLSI systems.…”