Caching and other latency tolerating techniques have been quite successful in maintaining high memory system performance for general purpose processors. However, TLB misses have become a serious bottleneck as working sets are growing beyond the capacity of TLBs. This work presents one of the first attempts to hide TLB miss latency by using preloading techniques. We present results for traditional next-page TLB miss preloading - an approach shown to cut some of the misses. However, a key contribution of this work is a novel TLB miss prediction algorithm based on the concept of “recency”, and we show that it can predict over 55% of the TLB misses for the five commercial applications considered.

Current high performance computer systems use complex, large superscalar CPUS that interface to the main memory through a hierarchy of caches and interconnect systems. These CP U-centric designs invest a lo~ofpower and chip area to bridge the widening gap between CPU and main memory speeds. Yet, many large application do not operate well on these systems and are limited by the memory subsystem performance. This paper argues for an integrated system approach that uses less-powerful CPUS that are tightly integrated with advanced memory technologies to build competitive systems with greatly reduced cost and complexity. Based on a design study using the next generation O.25~, 256Mbit dynamic random-access memory (DRAM) process and on the analysis of existing machines, we show that processor memory integration can be used to build competitive, scalable and cost-effective h4P systems, We present results from execution driven uni-and multi-processor simulationsshowing that the benejits of lower latency and higher bandwidth can compensate for the restrictions on the size and complexity of the integrated processor In this system, small direct mapped instruction caches with long lines are very effective, as are column buffer data caches augmented with a victim cache.