The scaling down of modern devices beyond 15 nm has faced major setbacks as it engendered short channel effects which were seemingly inexorable. One of the solutions proposed was to replace the conventional silicon channel with carbon nanotubes (CNTs), giving rise to the carbon nanotube field-effect transistor (CNTFET). CNTs provide unrivaled electrical and mechanical properties which make them an attractive alternative to silicon for channel materials. In this research work, a cylindrical gate CNTFET model is proposed, and its performance is studied and compared with existing experimental results. The performance of the device due to the variation in the doping profile of the source and drain is studied to realize a device that can manifest superior characteristics compared with existing devices. A model with a non-uniform doping profile is proposed that results in a significant reduction in leakage current. The characteristics upon which the performance is evaluated are the on/off current ratio (I ON/I OFF), subthreshold swing (SS), and threshold voltage. By adjusting various parameters, a device is constructed with I ON/I OFF of 4 × 106, SS of 63 mV dec−1 (approximately), and a threshold voltage of 0.45 V, which performs better than existing devices shown in the literature. All the simulations have been performed by employing the nonequilibrium Green’s function formalism with the self-consistent solution of the Schrödinger and Poisson equations.

Junctionless tunneling field-effect transistor (JL-TFET) is an excellent potential alternative to conventional MOSFET and TFET due to the lack of a steep doping profile, which makes it easier to fabricate. JL-TFET not only offers a lower subthreshold swing (SS) compared to MOSFET, but mitigates the low on-current problem associated with conventional TFET. The DC and analog characteristics of JL-TFET can be further improved by design modifications. In this research, we have presented two novel structures of JL-TFET: stimulated n-pocket JL-TFET (SNPJL-TFET) and SNPJL-TFET with heterogeneous gate dielectric. The performance of these devices has been gauged against conventional JL-TFET. Both novel structures exhibit excellent performance including point SS around 20 mV/dec, high I ON/I OFF in the order of 1014 and lower threshold voltage (V T). By analyzing RF and linearity parameters such as the transconductance generation factor, F T, transit time, total factor productivity, second-order voltage intercept point, third-order voltage intercept point, third-order input intercept point and third-order intermodulation distortion, it is observed that the proposed devices are more suitable for RF applications since they show superiority in most of the analyzed parameters.

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In this research work, a n-type silicon tunneling field effect transistor (TFET) has been designed and investigation has been carried out on its performances by altering different device parameters such as gate insulator dielectric constant, channel thickness, gate geometry, and channel length. The performances have been evaluated based on subthreshold swing, threshold voltage and I on /I off ratio of the devices. The goal is to find a device which would simultaneously have a low subthreshold swing (SS), low threshold voltage, and a high I on /I off ratio. It has been observed that having a double gate, short channel length, high-k dielectric, and low channel thickness leads us towards a compact design and the device exhibits very promising values of the aforementioned performance criteria. The most attractive proposition about a TFET is its ability to have a subthreshold swing lower than 60 mV/dec which is the theoretical limit of a MOSFET. In this study, an optimized device is obtained which has a subthreshold swing (point) of around 26 mV/dec and an I on /I off ratio in the order of 1013. In addition, an inverter has been designed using a n-type TFET and a resistor to show the potential of TFETs to be used in logic circuits.

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