No abstract

No abstract

Firstly an embedded 55-nm Flash design based on split-gate Flash bitcell is proposed by 32KX64 IP. It demonstrates competitive features for production by wide voltage supply range (VDD=0.86~1.32V, and VD25=1.6~3.6V), low-power read feature (96uA/MHz, 64 bits), fast wake-up time from power off (< 2us), and fast operation read speed up to 75MHz (VDD=1.08V).

In this paper, a case of package level reliability test failure was studied. A model of “Slice Defect”, which was identified as the root cause by failure analysis, is introduced. Experiment results are presented to approve that such model is in fact correct and the corrective actions are effective.

In reliability test some chips suffered functional failure. Through a series of failure analysis experiments, the root cause was determined to be a silicon dislocation across LDD (Lightly Doped Drain) area causing p-n junction leakage. However, those failed samples all passed both CP (Chip Probe) and FT (Final Test) monitor. Therefore, it is reasonable to suspect that DVS (dynamic voltage stress) may enhance minor dislocations already existing before CP and FT. To prove this hypothesis, an experiment was designed to find the relationship between DVS and the depth of dislocation in silicon substrate. In conclusion, DVS could enhance dislocation across LDD area, which may induce reliability failure. Moreover, reliability concerns on this finding will be discussed in this paper.