-This paper proposes a new real-time 2-D convolver filter chip without using any parallel multiplier. The proposed chip uses only one special shift-and-accumulation block instead of nine multipliers. Hence the chip can reduce the chip size by more than 70% of commercial 2-D convolver chips. Moreover, the proposed chip does not require row buffers to control input data sequence employed in commercial chips. We implemented the filter chip using the 0.8µm SOG cell library (KG60K). The filter chip consists of only 3,893 gates, operates at 125 MHz and can meet the real-time image processing requirement, i.e., the standard of CCIR601.

This paper proposes an architecture for the high-speed WLAN MODEM ASIC chip. The architecture supports the DSSS physical layer specifications in the IEEE 802.11. The spread sequence can be extended up to 16 chips, the number of samples per chip is 2, and the maximum data rate is 4Mbps. The proposed modem supports various data rates, Le., 4Mbps, 2Mbps and lMbps and provides DBPSK and DQPSK for data modulation. We have simulated algorithm models using the SPWTM and verified the BER performance in AWGN channel environments and the carrier frequency offset and clock offset environments. The proposed architecture shows lower BER than Harris HSP3824. The proposed modem chip is being fabricated using the Samsungm 0.6 pm gate array library.