An efficient 2-D convolver chip for real-time image processing

Abstract

-This paper proposes a new real-time 2-D convolver filter chip without using any parallel multiplier. The proposed chip uses only one special shift-and-accumulation block instead of nine multipliers. Hence the chip can reduce the chip size by more than 70% of commercial 2-D convolver chips. Moreover, the proposed chip does not require row buffers to control input data sequence employed in commercial chips. We implemented the filter chip using the 0.8µm SOG cell library (KG60K). The filter chip consists of only 3,893 gates, operates at 125 MHz and can meet the real-time image processing requirement, i.e., the standard of CCIR601.

QRS detection algorithm on a novel reconfigurable multiplierless architecture

“…Furthermore, for an 8b input sequence, the filter having N=36, will contain thirty-six 8x8 bit multipliers. Following the multiplication, one would need a 16-b tree adder to add the multiplication results and is not area efficient [4]. In [9] authors have shown that for very low voltage and very low power applications, reducing the number of gates and the critical path is beneficial.…”

“…Since multipliers occupy a large area, a digital signal processor without any multipliers can be implemented with significantly reduced area. Several multiplierless architectures have been proposed in the literature [3], [4]. In [4], the multiplierless architecture with an n tap filter replaces n multipliers with n shift-and-accumulation (SA) blocks.…”

“…Several multiplierless architectures have been proposed in the literature [3], [4]. In [4], the multiplierless architecture with an n tap filter replaces n multipliers with n shift-and-accumulation (SA) blocks. However due to large number of shift and accumulate (SA) operations, these architectures still require relatively large area.…”