With the development of science and technology, the feature size of CMOS devices will always shrink to the limit. Therefore, some new nanodevices will eventually become substitutes for microelectronic devices. A new electronic revolution will break out. Nanoscience and technology is the high-tech frontier technology of the century and one of the main contents of scientific development in the new era. Its development will have a profound impact on other disciplines, industries, and society. Nanoelectronics is an important part of the discipline of nanoscience and technology, which represents the development trend of microelectronics and will become the foundation of the next generation of electronic science and technology. With the development of ultra-large-scale integrated circuits, the feature size of electronic devices is getting smaller and smaller and has entered the nanoscale from the microscale. When the size of the system is small enough to be compared with the wavelength of electrons, the quantum effect becomes the dominant current-carrying main factor in child behavior. While these new phenomena and new effects bring challenges to the original semiconductor devices, they also provide opportunities for the development of new devices. Evolutionary circuit design is based on cellular neural network and quantum-dot cells, designs combinational logic circuits through the evolutionary algorithm, uses the logic gate based on cellular neural network design as the population gene of evolutionary circuit design, enriches the diversity of the population, and improves the evolutionary algorithm at the same time, the success rate of the improved genetic algorithm for evolutionary circuits has been greatly improved, and the failure rate has been reduced from 14% to 2%, obtaining a faster evolution speed and improving the performance of the evolution circuit.

No abstract

No abstract

The design of this paper is a 12bit SAR ADC,in order to optimize its performance and be able to achieve high accuracy, there are certain requirements for certain modules of the ADC. The design uses the bottom plate sampling, access to the common mode level Vcm on the upper pole plate of the DAC capacitor array is accessed by a higher precision bootstrap switch to reduce the non-linearity brought by the Vcm level access switch. By performing FFT simulation on the sampling points, it can be used at a sampling rate of 50Ms/s when the input signal frequency is 0.8301MHz and ENOB is 15.64bit. The capacitor array uses a combination of segmentation and splitting to greatly reduce the number of total capacitors, achieving only 188 unit capacitors, a 97.7% reduction in number compared to the conventional structure, for the entire ADC digital circuit The power consumption as well as the area of the ADC digital circuit has been significantly improved. The comparator uses a dynamic latching comparator to reduce power consumption while reducing the equivalent input noise of the comparator. The logic circuit uses dynamic SAR logic to control the analog-to-digital converter's successive comparisons. Sampling and analysis of the entire SAR ADC output achieves a valid bit count of 11.93 bits at a low frequency input signal of 0.1953MHz, enabling the conversion of a 12bit SAR ADC.