Double Patterning lithography is very fascinating way of lithography which is capable of pushing down the k1 limit below 0.25. By using double patterning lithography, we can delineate the pattern beyond resolution capability. Target pattern is decomposed into patterns within resolution capability and decomposed patterns are combined together through twice lithography and twice etch processes. Two ways, negative and positive, of doing double patterning process are contrived and studied experimentally. In this paper, various issues in double patterning lithography such as pattern decomposition, resist process on patterned topography, process window of 1/4 pitch patterning, and overlay dependent CD variation are studied on positive and negative tone double patterning respectively. Among various issues about double patterning, only the overlay controllability and productivity seemed to be dominated as visible obstacles so far.

Double patterning lithography has been one of the candidates for sub-40nm patterning era, and has a lot of process issues to be confirmed. Last year, we presented the issues in double patterning lithography with a real flash gate pattern. Process flow was suggested and CD uniformity due to overlay was analyzed. And the layout decomposition and the two types of double patterning of positive and negative tone were studied with 1-dimensional pattern. In this paper, the implementation to DRAM patterns is examined, which consist of 2-dimensional patterns. Double patterning methods and the selection of their tone for each layer are studied, and the difficulties from the randomness of core pattern are also considered. As a result, DRAM patterns have more restrictions on the double patterning method and selection of tone, and the aggressive layout decomposition should be designed to solve the difficulty in core patterning. Therefore, 37nm DRAM layout can be patterned and the overlay control and cost still remain as dominant obstacles.

5l2Mbit DRAM with 7Onm design rule was tailored using 0.3 iki ArF lithography technologies. Of the critical mask layers, four pattern layouts were demonstrated: brick wall, line/space, contact and line/contact patterns. For the sake of cost reduction, the conventional technologies were used. Results has shown that SLR(Single-Layer Resist) process, halftone PSM and the conventional illuminations had a potential of manufacturing 7Onm DRAM. However, it was found that brick w all patterns had asymmetrical s hape and total CD u niformity w as out of target r aging 9.2nm through l6.3nm depending mask 1 ayouts. W e p rospect t hat h igher c ontrast r esist a nd more e laborate r esist p rocess will a ddress t hese problems sooner or later. In case the immersion lithography is not ready around the right time, the feasibility of O.29k1 ArF lithography was studied through simulation and test, which represented that O.29k1 technologies were likely to be applied for the development of 6Onm DRAM with the aid of RETs(Resolution Enhancement Technologies) including customized illumination and new hard mask process.

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