A thin palladium layer (∼40 Å) was selectively formed on top of amorphous silicon films before annealing and the effects of palladium layer on the crystallization behavior of the amorphous silicon films were investigated. It was observed that the amorphous silicon right under the Pd layer could be crystallized to grain sizes of several hundred angstroms by annealing at 500 °C. In addition, the area between the Pd thin pads, patterned by lithography, was found to be crystallized to grain sizes of a few tens of microns in length by the same annealing. Such lateral crystallization was found to reach more than 100 μm in some cases. The lateral crystallization phenomenon might be useful for the fabrication of low temperature polycrystalline-Si thin film transistors, providing large-grained Si films.

Low-temperature activation of dopants in amorphous silicon films was achieved by a new method and high-performance polycrystalline silicon thin film transistors were fabricated through its application. It was found that the dopants implanted into amorphous silicon were activated simultaneously with the crystallization of amorphous silicon. With the help of a thin nickel layer, the thermal budget for dopant activation and crystallization was considerably reduced, from 600 °C (30 h) to 500 °C (5 h). Even without plasma hydrogenation, the n-channel polycrystalline silicon thin film transistors fabricated at temperatures below 500 °C showed a mobility of 120 cm2/V s, which is much higher than that of conventional devices fabricated at 600 °C.