This paper presents a 100 kS/s, 1.3 W, 9.3 ENOB successive approximation ADC with a time-domain comparator. The proposed time-domain comparator utilizes a differential multi-stage VCDL, resulting in a highly digital operation eliminating static power consumption. The effects of gain, noise, and offset are also investigated by detailed analysis which proves the feature of reducing the input-referred noise and offset by simply increasing the number of delay stages. For verification, the proposed ADC is fabricated in a 0.18 m CMOS. With a single supply voltage of 0.6 V, the ADC consumes 1.3 W at the maximum sampling rate of 100 kS/s. The measured ENOB is 9.3 b showing a figure of merit of 21 fJ/conversion-step.

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This paper presents a low-power resistive sensor interface circuit with correlated double sampling which reduces the effect of amplifier offset and enables time-interleaved singleto-differential sampling. The proposed sampling scheme, used with a 12b SAR-type analog-to-digital converter, effectively doubles the input signal and improves linearity. The fabricated chip in 0.13μm CMOS demonstrates a sampling rate of 1-kS/s and a dynamic range of 117dB with a maximum conversion error of 0.32-percent while consuming only 11.3-μW from single supply voltage of 0.5V.

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