Bandgap references (BGRs) are widely used to generate a temperatureinsensitive reference voltage determined by the silicon bandgap. The BGR generally utilizes PN diodes to generate both of proportional-to-absolutetemperature (PTAT) and complementary-to-absolute-temperature (CTAT) quantities and combines them to eliminate the temperature dependency. Though the BGR provides a robust voltage or current reference with insensitivity to process, voltage and temperature variations that is superior to CMOS-only reference circuits, it has received little attention in ultra-low-power (ULP) sensor applications. While CMOS-only reference circuits have recently demonstrated nanowatt power consumption [1], BGR approaches still have two critical factors to preventing nanowatt consumption. One is that PTAT generation assumes sufficient forward bias, VD, of the PN junction to allow e VD/(n⋅VT) to be much larger than 1 in the temperature range of interest, where n and VT (=kT/q) represent the ideality factor and the thermal voltage, respectively. In addition, the PTAT generation requires a start-up circuit to prevent the circuit from resting at the undesirable zero-bias condition. Since the start-up circuit utilizes a resistive voltage division between power rails, it consumes non-zero DC current, which must be larger than leakage current in order to ensure stable start-up operation. These two requirements for PTAT generation limit the use of BGRs in nanowatt ULP applications.Recently, a sample-and-hold scheme with duty cycling was applied to a BGR circuit and achieved a power consumption of a few nanowatts [2]. However, it uses a traditional BGR core and does not reduce the power consumption of the BGR circuit itself when it is turned on. Therefore, further reduction of power consumption would be achieved if a similar sample-and-hold scheme were applied to a more energy-efficient BGR core. It also requires a large silicon area to implement sampling capacitors. Resistor-less PTAT schemes with cascaded source-coupled pairs have been another approach to achieve sub-μW BGRs [3,4]. However, these suffer from degraded performance in temperature sensitivity and line regulation due to increased dependency on transistor characteristics. This paper proposes a BGR with a leakage based PTAT. Without any start-up circuit, duty-cycling, or assumption of strong forward bias for the PTAT, the fabricated BGR in 0.35μm CMOS consumes 29nW at room temperature and shows a temperature coefficient of 12.75ppm/°C with a line regulation of 0.198%/V. Figure 5.7.1 shows the proposed concept of two-diode PTAT generation. The two diodes are identical except for a multiplication factor, L, determined by the ratio of the numbers of identical diodes used at pull-up and pull-down sides. The diodes are connected in series between power rails with the upper diode reverse biased. Then, only leakage current, L⋅Is, flows through the branch, where Is represents the reverse saturation current. The intermediate node voltage becomes PTAT, nV T ln(L+1), without the assump...
