A 1.2 V 20 nm 307 GB/s HBM DRAM With At-Speed Wafer-Level IO Test Scheme and Adaptive Refresh Considering Temperature Distribution

Sohn, Kiwon; Wang, Yun; Oh, Reum; Oh, Chisung; Seo, Seong-Young; Park, Min Sang; Shin, Dong‐Hui; Jung, W.W.; Shin, Sanghoon; Ryu, Je-Min; Yu, Hye-Seung; Jung, Jaehun; Lee, Hyunui; Kang, Sang Bom; Sohn, Young-Soo; Choi, Jung-Hwan; Bae, Young‐Seuk; Jang, Seong-Jin; Jin, Gyoyoung

doi:10.1109/jssc.2016.2602221

Cited by 51 publications

(22 citation statements)

References 1 publication

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“…Even in the case of multilayers' stacking, such as 33 (32 + 1) layers, the stacked DRAM device yield of close to 100% can be expected with a penalty of just one extra layer addition. If the device design provides smaller granularity of bank configuration (means more banks), such as 64 banks or more, the productivity should be better [9].…”

Section: B Case Where Single-layer Die Yield Is Greater Than or Equamentioning

confidence: 99%

Vertically Replaceable Memory Block Architecture for Stacked DRAM Systems by Wafer-on-Wafer (WOW) Technology

Sugatani

Chujo

Sakui

et al. 2020

IEEE Trans. Electron Devices

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This article proposes a 3-D-based redundancy scheme for the stacked dynamic random-access memory (DRAM) systems, which enables highly efficient productivity with the wafer-on-wafer (WOW) technology. Vertically replaceable block scheme and redundantly added wafer stack(s) are the keys of this technique. Memory bank replacement of the vertical combinations is taken into consideration. Random defect yield loss, which is a fundamental barrier for both the WOW technology and the leading-edge technologies, is dealt with in this study. Not only 4, 8, and 12 layers, but also 17 (16 + 1), 25 (24 + 1), and 33 (32 + 1) layers can be targeted. Therefore, this technique makes the WOW technology as another system scaling enabler.

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Section: B Case Where Single-layer Die Yield Is Greater Than or Equamentioning

confidence: 99%

Vertically Replaceable Memory Block Architecture for Stacked DRAM Systems by Wafer-on-Wafer (WOW) Technology

Sugatani

Chujo

Sakui

et al. 2020

IEEE Trans. Electron Devices

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“…High bandwidth memories like HBM2 [27] help in alleviating the memory bottleneck of memory bounded applications. We propose to use the 3D-stacked HBM2 memory for such workloads, attaining a bandwidth of 307.2 GB/s.…”

Section: High Bandwidth Memoriesmentioning

confidence: 99%

“…This leads to a performance benefit of 50%, 10.5% and 14% for Bowtie2, BWA-MEM and HISAT2, respectively, with corresponding energy savings of up to 53%, 18% and 26%, respectively. This is due to the fact that the three NGS applications are memory bounded and, therefore, benefit from high memory BW of up to 307.2 GB/s [27], which is provided by HBM2. We also observe that the performance and energy benefits of using HBM2 are more for OoO cores compared to in-order, as OoO cores can exploit more BW and therefore, take more advantage of HBM2.…”

Section: Number Of Coresmentioning

confidence: 99%

“…In this paper, we propose and utilize a design space exploration methodology to find performance, energy and area optimized architectures for the NGS application domain. Using this methodology we propose an optimized architecture based on 3D-stacked high bandwidth memory (HBM2) [27] alongside energy efficient ARMv8 64-bit compute cores. We use the gem5-X [28] architectural simulator, an open source, validated and enhanced version of gem5 [29], with HBM2 memory model.…”

Section: Introductionmentioning

confidence: 99%

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Genome Sequence Alignment - Design Space Exploration for Optimal Performance and Energy Architectures

Qureshi

Herruzo

Zapater

et al. 2020

IEEE Trans. Comput.

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Next generation workloads, such as genome sequencing, have an astounding impact in the healthcare sector. Sequence alignment, the first step in genome sequencing, has experienced recent breakthroughs, which resulted in next generation sequencing (NGS). As NGS applications are memory bounded with random memory access patterns, we propose the use of high bandwidth memories like 3D stacked HBM2, instead of traditional DRAMs like DDR4, along with energy efficient compute cores to improve both performance and energy efficiency. Three state-of-the-art NGS applications, Bowtie2, BWA-MEM and HISAT2, are used as case studies to explore and optimize NGS computing architectures. Then, using the gem5-X architectural simulator, we obtain an overall 68% performance improvement and 71% energy savings using HBM2 instead of DDR4. Furthermore, we propose an architecture based on ARMv8 cores and demonstrate that 16 ARMv8 64-bit OoO cores with HBM2 outperforms 32-cores of Intel Xeon Phi Knights Landing (KNL) processor with 3D stacked memory. Moreover, we show that by using frequency scaling we can achieve up to 59% and 61% energy savings for ARM in-order and OoO cores, respectively. Lastly, we show that many ARMv8 in-order cores at 1.5GHz match the performance of fewer OoO cores at 2GHz, while attaining 4.5x energy savings.

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“…As a second case study to demonstrate gem5-X architectural extension capabilities, we implement a High Bandwidth Memory (HBM) based on 3D die stacking technology. We implement the HBM2 memory model as proposed by Sohn et al (2017), which has bandwidth of 307 GB/s in comparison to 25.2 GB/s for DDR4 architectures described by Hsueh et al (2014) to alleviate the memory bottlenecks generated due to the concurrent run of multiple memory bounded applications.…”

Section: Introductionmentioning

confidence: 99%

Gem5-X: A Gem5-Based System Level Simulation Framework to Optimize Many-Core Platforms

Qureshi

Simon

Zapater

et al. 2019

2019 Spring Simulation Conference (SpringSim)

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The rapid expansion of online-based services requires novel energy and performance efficient architectures to meet power and latency constraints. Fast architectural exploration has become a key enabler in the proposal of architectural innovation. In this paper, we present gem5-X, a gem5-based system level simulation framework, and a methodology to optimize many-core systems for performance and power. As real-life case studies of many-core server workloads, we use real-time video transcoding and image classification using convolutional neural networks (CNNs). Gem5-X allows us to identify bottlenecks and evaluate the potential benefits of architectural extensions such as in-cache computing and 3D stacked High Bandwidth Memory. For real-time video transcoding, we achieve 15% speed-up using in-order cores with in-cache computing when compared to a baseline in-order system and 76% energy savings when compared to an Out-of-Order system. When using HBM, we further accelerate real-time transcoding and CNNs by up to 7% and 8% respectively.

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A 1.2 V 20 nm 307 GB/s HBM DRAM With At-Speed Wafer-Level IO Test Scheme and Adaptive Refresh Considering Temperature Distribution

Cited by 51 publications

References 1 publication

Vertically Replaceable Memory Block Architecture for Stacked DRAM Systems by Wafer-on-Wafer (WOW) Technology

Vertically Replaceable Memory Block Architecture for Stacked DRAM Systems by Wafer-on-Wafer (WOW) Technology

Genome Sequence Alignment - Design Space Exploration for Optimal Performance and Energy Architectures

Gem5-X: A Gem5-Based System Level Simulation Framework to Optimize Many-Core Platforms

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