We had previously established CP (character projection) based EBDW technology for 65nm and 45nm device production [1] [2]. And recently we have confirmed the resolution of 14nm L&S patterns which meets 14nm and beyond node logic requirement with CP exposure [3]. From these production achievement and resolution potential, with multi-beam EBDW and CP function, MCC [4] could be one of the most promising technologies for future high volume manufacturing if exposure throughput was drastically enhanced. We have set target throughput as 100 WPH to meet HVM (high volume manufacturing) requirement. Our designed parameters to attain 100 WPH for 14nm result in 150 beams, 10cluster, 100 Giga shots/wafer, 250A/cm^2 and 75uC/cm^2.In addition to multi-beam, drastic exposure shot reduction is indispensable to attain 100 WPH for 14nm node. We have aggressively targeted 100 Giga shot count which is equivalent to covering 300mm wafer with 0.8um x 0.8um square fairly large tile. All device circuit blocks should be structured with only CP defined parts and we should trace back to upstream design flow to RTL. We call this methodology "CP element based design". In near future, Litho-Friendly restricted design would be commonly used [5] [6]. Our CP defined tile based regular layout would be highly compatible with these ultra-regular design approaches. The primal design factors are Logic cell, Memory macro and random interconnect. We have established concepts to accomplish high volume production with CP-based EBDW at 14nm technology node.

When manufacturing prototype devices or low volume custom logic LSIs, the products are being less profitable because of the skyrocketing mask and design costs recent technology node. For 65nm technology node and beyond, the reduction of mask cost becomes critical issue for logic devices especially. We attempt to apply EBDW mainly to critical interconnect layers to reduce the mask expenditure for the reason of technical output reusability.For 65nm node production, new 300mm EB direct writer had been installed. The process technologies have also been developing to meet sufficient qualities and productivities.

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A detailed investigation has been carried out into the evolution of grain size and grain orientation in electroplated Cu interconnection lines. The specimens were annealed to produce a range of different grain size distributions. Very accurate grain size distributions were obtained from extensive TEM observations of a large number of specimens, followed by computer tracing of grain boundaries. Although annealing causes the average grain size to increase, very small grains are found to persist in the distribution, even when the average grain size is large. These small grains have been investigated in detail to determine the reason for their thermal stability. In addition, the occurrence and redistribution of small micro-voids has been investigated for wafers with different grain sizes. These voids are believed to be associated with seams which are formed in the Cu lines during plating.