Bumpless Build Cube (BBCube): High-Parallelism, High-Heat-Dissipation and Low-Power Stacked Memory using Wafer-Level 3D Integration Process

Chujo, Norio; Sakui, Koji; Ryoson, Hiroyuki; Sugatani, Shinji; Nakamura, Tomoji; Ohba, Takayuki

doi:10.1109/vlsitechnology18217.2020.9265038

Cited by 6 publications

(12 citation statements)

References 6 publications

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“…The electrical characteristics of the BBCube structure were calculated by 3D EM field analysis and compared to conventional 3D integration (3DI) with micro-bumps [34]. The TSV model used for conventional 3DI with micro-bumps, such as HBM, is shown in Figure 30a, and the TSV model used for BBCube is shown in Figure 30b.…”

Section: Electrical Characteristics Of Bbcubementioning

confidence: 99%

“…Circuit simulation was used to estimate the power consumption of the I/O circuit. An eye diagram was calculated, and the I/O current that satisfies the eye mask was determined [34]. The structure of BBCube is presented in Figure 32 and a block diagram of the simulation is shown in Figure 33a.…”

Section: Electrical Characteristics Of Bbcubementioning

confidence: 99%

“…In the stacked memory as a whole, BBCube could realize a four-times higher bandwidth with only 13% of the I/O power consumption compered to HBM, as shown in Circuit simulation was used to estimate the power consumption of the I/O circuit. An eye diagram was calculated, and the I/O current that satisfies the eye mask was determined [34]. The structure of BBCube is presented in Figure 32 and a block diagram of the simulation is shown in Figure 33a.…”

Section: Electrical Characteristics Of Bbcubementioning

confidence: 99%

“…As for the I/O power consumption, the first target of the bumpless HBM was one-thirtieth that of the current HBM2 [28], as shown in Figure 38. Figure 39 compares HBM2 with bumps [31][32][33] and bumpless HBM with respect to their data bandwidth and I/O buffer power, according as the number of I/O's [28,29,34,92,93]. Figure 39 compares HBM2 with bumps [31][32][33] and bumpless HBM with respect to their data bandwidth and I/O buffer power, according as the number of I/O's [28,29,34,92,93].…”

Section: Competitive Bbcube Dram Structurementioning

confidence: 99%

“…In detail, the z-height of a multi-wafer stack must be small, meaning that there should be no bumps between dies, and the dies should be thin. This is the main feature of BBCube, which allows high bandwidth with low power consumption because of the short length of TSVs and high-density signal parallelism [34]. Furthermore, high-density TSVs act as thermal pipes, and, hence, a low temperature, even in a 3D structure, can be expected.…”

Section: Introductionmentioning

confidence: 99%

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Review of Bumpless Build Cube (BBCube) Using Wafer-on-Wafer (WOW) and Chip-on-Wafer (COW) for Tera-Scale Three-Dimensional Integration (3DI)

et al. 2022

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Bumpless Build Cube (BBCube) using Wafer-on-Wafer (WOW) and Chip-on-Wafer (COW) for Tera-Scale Three-Dimensional Integration (3DI) is discussed. Bumpless interconnects between wafers and between chips and wafers are a second-generation alternative to the use of micro-bumps for WOW and COW technologies. WOW and COW technologies for BBCube can be used for homogeneous and heterogeneous 3DI, respectively. Ultra-thinning of wafers down to 4 μm offers the advantage of a small form factor, not only in terms of the total volume of 3D ICs, but also the aspect ratio of Through-Silicon-Vias (TSVs). Bumpless interconnect technology can increase the number of TSVs per chip due to the finer TSV pitch and the lower impedance of bumpless TSV interconnects. In addition, high-density TSV interconnects with a short length provide the highest thermal dissipation from high-temperature devices such as CPUs and GPUs. This paper describes the process platform for BBCube WOW and COW technologies and BBCube DRAMs with high speed and low IO buffer power by enhancing parallelism and increasing yield by using a vertically replaceable memory block architecture, and also presents a comparison of thermal characteristics in 3D structures constructed with micro-bumps and BBCube.

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Section: Electrical Characteristics Of Bbcubementioning

confidence: 99%

Section: Electrical Characteristics Of Bbcubementioning

confidence: 99%

Section: Electrical Characteristics Of Bbcubementioning

confidence: 99%

Section: Competitive Bbcube Dram Structurementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Review of Bumpless Build Cube (BBCube) Using Wafer-on-Wafer (WOW) and Chip-on-Wafer (COW) for Tera-Scale Three-Dimensional Integration (3DI)

et al. 2022

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FEA Simulations for Thermal Distributions of Large Scale 3DIC Packages

Chen,

Wu,

Xun

et al. 2024

IEEE Access

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As the market increases for Artificial Intelligence and High-Performance Computing applications, the geometry of 3-Dimensional Integrated Circuit packages becomes more complicated; therefore, predicting the thermal distributions of the structures becomes not only more important but also more challenging. The physics governing the thermal distribution is a 3-dimensional partial differential equation. In order to predict the thermal distributions, various approaches such as the layer modeling method have been invented. While practical, these approaches solve a simplified version of the differential equation placing an inherent limitation on their capabilities which may be improved upon. In this research we solve the actual differential equation using Finite Element Analysis. Finite Element Analysis is known to produce accurate solutions, albeit being computationally intensive, and may take days to run even with a powerful computer, making it impractical for some applications. In this paper, we present case studies of computing the thermal distributions of large scale 3-dimensional integrated circuit models using XSim. We find that XSim's solving capabilities are capable of computing accurate thermal distributions of large-scale models in minutes instead of days. This suggests a new way to compute the thermal distributions rapidly and accurately for large 3-Dimensional Integrated Circuit packages, which may bring potential benefits in research, design and development of 3-Dimensional Integrated Circuit packages.

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Electrical and Thermal Analysis of Bumpless Build Cube 3D Using Wafer-on-Wafer and Chip-on-Wafer for Near Memory Computing

Chujo

Ryoson

Sakui

et al. 2023

2023 IEEE 73rd Electronic Components and Technology Conference (ECTC)

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Bumpless Build Cube (BBCube): High-Parallelism, High-Heat-Dissipation and Low-Power Stacked Memory using Wafer-Level 3D Integration Process

Cited by 6 publications

References 6 publications

Review of Bumpless Build Cube (BBCube) Using Wafer-on-Wafer (WOW) and Chip-on-Wafer (COW) for Tera-Scale Three-Dimensional Integration (3DI)

Review of Bumpless Build Cube (BBCube) Using Wafer-on-Wafer (WOW) and Chip-on-Wafer (COW) for Tera-Scale Three-Dimensional Integration (3DI)

FEA Simulations for Thermal Distributions of Large Scale 3DIC Packages

Electrical and Thermal Analysis of Bumpless Build Cube 3D Using Wafer-on-Wafer and Chip-on-Wafer for Near Memory Computing

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