Review of Bumpless Build Cube (BBCube) Using Wafer-on-Wafer (WOW) and Chip-on-Wafer (COW) for Tera-Scale Three-Dimensional Integration (3DI)

Abstract

Bumpless Build Cube (BBCube) using Wafer-on-Wafer (WOW) and Chip-on-Wafer (COW) for Tera-Scale Three-Dimensional Integration (3DI) is discussed. Bumpless interconnects between wafers and between chips and wafers are a second-generation alternative to the use of micro-bumps for WOW and COW technologies. WOW and COW technologies for BBCube can be used for homogeneous and heterogeneous 3DI, respectively. Ultra-thinning of wafers down to 4 μm offers the advantage of a small form factor, not only in terms of the total volume of 3D ICs, but also the aspect ratio of Through-Silicon-Vias (TSVs). Bumpless interconnect technology can increase the number of TSVs per chip due to the finer TSV pitch and the lower impedance of bumpless TSV interconnects. In addition, high-density TSV interconnects with a short length provide the highest thermal dissipation from high-temperature devices such as CPUs and GPUs. This paper describes the process platform for BBCube WOW and COW technologies and BBCube DRAMs with high speed and low IO buffer power by enhancing parallelism and increasing yield by using a vertically replaceable memory block architecture, and also presents a comparison of thermal characteristics in 3D structures constructed with micro-bumps and BBCube.

High-Density Solid-State Memory Devices and Technologies

“…The sixth review paper in the Special Issue is by Ohba et al [6] and summarizes the state-of-the-art of the Bumpless Build Cube (BBCube) using a Wafer-on-Wafer (WOW) and a Chip-on-Wafer (COW) approach, representing a new process solution for Tera-Scale Three-Dimensional Integration (3DI). In the paper, the BBCube architecture is explicitly considered for memory applications, considering BBCube DRAM and BBCube NAND Flash solutions.…”

Minimizing die fracture in 3DIC die integration

“…The vertically stacked die connected with TSVs became the 3D package. Ohba et al 6 provided a review for TSVs used in stacked wafers. An improved variation of the 3D system included increasing the number of stacked dies, causing other reliability issues, such as mechanical stresses, which require thinner dies.…”

“…The vertically stacked die connected with TSVs became the 3D package. Ohba et al 6 . provided a review for TSVs used in stacked wafers.…”

“…The 2019 Heterogeneous Integration Roadmap 10 predicts that a 10-die stack for dies with thicknesses of 25 μm and a 50-die stack for dies with thicknesses of 5 μm is possible using a 5-μm die-attach film all with a 600 μm package profile. In the more advanced technologies, using copper–copper solderless direct connect for wafer-on-wafer (WOW), it is estimated that an eight-wafer stack can be done with <80 μm 6 and a 60 wafers stack with <500 μm 6 using the chip pitch as an estimator. TechInsights 11 has shown cross-sections of Sony’s CMOS image sensor stacked die to form one product from two distinct process flows, such as connecting a 90 nm die with a 65 nm die through TSV connections.…”