EBDW technology for EB shuttle at 65nm node and beyond

Maruyama, Takashi; Takakuwa, Masaki; Kojima, Yoshinori; Takahashi, Yoshiaki; Yamada, Kazuhiko; Kon, Junichi; Miyajima, M.; Shimizu, Akihiro; Machida, Yasuhide; Hoshino, Hiromi; Takita, Hiroshi; Sugatani, Shinji; Tsuchikawa, H.

doi:10.1117/12.772469

Cited by 15 publications

(15 citation statements)

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“…Transistor stacking is considered a special type of chaining. Stacks have an advantage over regular chaining in that they do not need a contact and, consequently, might improve the layout density in some process technologies 3 . Therefore, if multiple chaining solutions have the maximum number of abutments, we pick the one with the maximum number of stacks.…”

Section: Variant Of Bipartite Matching W/ Clusteringmentioning

confidence: 99%

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DRE: A Framework for Early Co-Evaluation of Design Rules, Technology Choices, and Layout Methodologies

Ghaida

Gupta

2012

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Design rules have been the primary contract between technology developers and designers and are likely to remain so to preserve abstractions and productivity. While current approaches for defining design rules are largely unsystematic and empirical in nature, this paper offers a novel framework for early and systematic evaluation of design rules and layout styles in terms of major layout characteristics of area, manufacturability, and variability. The framework essentially creates a virtual standard-cell library and performs the evaluation based on the virtual layouts. Due to the focus on the exploration of rules at an early stage of technology development, we use first order models of variability and manufacturability (instead of relying on accurate simulation) and layout topology/congestion-based area estimates (instead of explicit and slow layout generation). Such a framework can be used to co-evaluate and co-optimize design rules, patterning technologies, layout methodologies, and library architectures.

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Section: Variant Of Bipartite Matching W/ Clusteringmentioning

confidence: 99%

“…On the patterning front, disruptive changes include the adoption of one or more of candidate next-generation lithography techniques such as nanoimprint, electron beam direct write, and extreme ultraviolet [1][2][3][4]. Each of these has challenging implications for layout methodologies and design rules (DRs).…”

Section: Introductionmentioning

confidence: 99%

DRE: A Framework for Early Co-Evaluation of Design Rules, Technology Choices, and Layout Methodologies

Ghaida

Gupta

2012

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…As for transistor locations along the vertical direction, we consider three possibilities: a) as near as possible to power rails, b) exactly in the center of p/n networks, and c) as near as possible to p/n interface. The choice of vertical location of transistors is regarded as a layout style, which can also be evaluated by the framework 3 .…”

Section: A Layout Topology Generationmentioning

confidence: 99%

“…On the patterning front, disruptive changes include adoption of one or more of candidate next-generation lithography techniques such as nanoimprint, electron beam direct write, and extreme ultraviolet [1][2][3][4]. Each of these has challenging implications for layout methodologies and design rules (DRs).…”

Section: Introductionmentioning

confidence: 99%

A framework for early and systematic evaluation of design rules

Ghaida

Gupta

2009

Proceedings of the 2009 International Conference on Computer-Aided Design

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Abstract-Design rules have been the primary contract between technology and design and are likely to remain so to preserve abstractions and productivity. While current approaches for defining design rules are largely unsystematic and empirical in nature, this paper offers a novel framework for early and systematic evaluation of design rules and layout styles in terms of major layout characteristics of area, manufacturability, and variability. Due to the focus on co-exploration in early stages of technology development, we use first order models of variability and manufacturability (instead of relying on accurate simulation) and layout topology/congestion-based area estimates (instead of explicit and slow layout generation). The framework is used to efficiently co-evaluate several debatable rules (evaluation for a 104-cell library takes 20 minutes). Results show that: a) diffusionrounding mainly from diffusion power-straps is a dominant source of variability, b) cell-area overhead of fixed gate-pitch implementation compared to 1D-poly implementation is tolerable (5%) given the improvement in variability, and c) 1D-poly restriction, which improves manufacturability and variability, has almost no area overhead compared to 2D-poly. In addition, we explore gate-spacing rules using our evaluation framework. This exploration yields almost identical values as those of a commercial 65nm process, which serves as a validation for our approach.

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“…In this paper, we focus on the frequency of the ring YCO circuits and, for an around 10 GHz YCO circuit, propose a design method based on a small-signal equivalent circuit analysis, in which the parasitic capacitors and resistances with input node are taken into consideration in more detail than in our previous work [7]. We compare the estimated and measured oscillation characteristics of ring YCO ICs fabricated with the 65-nm MOSFET process [8].…”

Section: Introductionmentioning

confidence: 99%

Analysis and design based on small-signal equivalent circuit for a lO-GHz ring VCO with 65-nm CMOS

Kishine

Inaba

Ohtomo

et al. 2013

2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS)

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An analysis and design method for a lO-GHz ring voltage-controlled oscillator (VCO) are proposed. By using a detailed small-signal equivalent circuit model, the delay of the current mode logic buffer circuit and the minimum limit of the number of those used in the VCO are evaluated. We set the transconductance generator in a MOSFET model as a function of drain current and obtained the current dependence of the oscillation frequency of the VCO. To confirm the validity of the design method, we compared the measured and estimated oscillation frequency of the VCO fabricated with the 65-nm MOSFET process. The agreement between the measurements and calculations is good enough, confirming the validity of the method.

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EBDW technology for EB shuttle at 65nm node and beyond

Cited by 15 publications

References 0 publications

DRE: A Framework for Early Co-Evaluation of Design Rules, Technology Choices, and Layout Methodologies

DRE: A Framework for Early Co-Evaluation of Design Rules, Technology Choices, and Layout Methodologies

A framework for early and systematic evaluation of design rules

Analysis and design based on small-signal equivalent circuit for a lO-GHz ring VCO with 65-nm CMOS

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