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I. ABSTRACTAn advanced 0.1 p m CMOS technology on SO1 is presented. In order to minimize short channel effects, relatively thick nondelpleted (0.1 p m ) SO1 film, highly non-uniform channel doping and source-drain extension-HALO were used. Excellent short channel effects (SCE) down to channel lengths below 0.1 p m werc obtained. Very high speeds wcre obtained: Unloaded dclay was 20 psec, and fully loaded NAND (FI=FO=3, C~= 0 . 3 pF) delay was 130 pscc at supply of 1.8 V.

I. ABSTRACTIn this paper a CMOS technology with the nominal channel length of 0.15 p m and minimum channel length below 0.1 p m is presented. Loaded NAND (FI=FO=3, Ct=240 f F ) delay of 200 psec and unloaded delay of 33 psec at supply voltage of 1.8 V is demonstrated. In order t o minimize short channel effects down to channel length below 0.1 p m , highly non-uniform channel doping obtained by indium and antimony, and source-drain extensions were utilized. To minimze the gate RC, a polycide stack gate structure was used. :[NTRODUCTION AND DESIGN POINTDeep submicron CMOS will be the main technology for ULSI systems. Figure 1 is a summary of the trend observed in CMOS scaling. As room temperature CMOS is scaled down below 0.35 p m , one is forced t o reduce the operating voltage of the MOS device due t o reliability and power constraints. Presently the state of .;he art CMOS is a 0.25 p m CMOS operating at 2.5 V [l]. Upo:n further scaling, the supply voltage should be dropped to about 1.5-2.2 V. The power supply choice depends on per-Tormance/reliability/power trade-offs. Reduced power supply allows scaling of the gate oxide within 4-5 nm range. It is estimated that for a 0.15 pm CMOS, devices with L~f f less than 0.1 p m should have acceptable threshold roll-off and off CUIrent. In this work in order t o contain the short channel effect (SCE), highly non-uniform channel doping [2], and very shallow junction/extensions were utilized. Highly non-uniform doping, allows high dopant concentration just below the channel in order to shield the drain field, and at the same time allows low device threshold (VT) and high mobility. Gate RC becomes a significant part of the circuit delay for submicron CMOS circuits. 13evices with both conventional salicide structure and a polycide structure (to reduce the resistance of the gate poly lines below 0.15 p m ) were fabricated. Figure :2 is a schematic cross section of a 0.15 p m CMOS: Both nMOS and PMOS are surface channel, twin well CMOS on p-/p+ epi. Gate oxide was 4.5 nm. E-beam lithography was used for the gate patterning in order to obtain channel lengths below 11.1 p m . Indium and antimony were used in order to obtain highly non-uniform channel implants in order to minimize SCE's. Background doping was 2-4x PROCESS TECHNOLOGYUltra-shallow extensions were obtained by pre-amorphization by indium and low energy As implant for nMOS and Sb pre-amorphization and BF2 for PMOS devices. Figure 3 is a typical profile used in nMOS and PMOS extensions and channel implants. The deep junctions is used for robust contact process. A thick spacer was formed in order to place the deep junction far from the channel. The gate stack was dual doped poly, followed by a thick sputtered Tis& and covered with dielectric to protect the polycide later in the process, or conventional salicided structure. The deep junctions were salicided t o minimize the source and drain sheet resistance. Figure 4 presents the device characteristics for 0.1 p m L~f f nMOS and PMOS. Figure 5 is the device characteristi...

The experimentally observed V, roll-off and Drain Induced Barrier Lowering (DIBL) at channel lengths of M 0.2pm in SiMOSFETs is underestimated by conventional 2D numerical simulations. In this paper it is shown that this is due to B segregation from the channel region towards the As-implanted source/drain regions during the As activation anneal. The resulting B depletion close to the source and drain lowers the local V, and contributes significantly (up to 50% in 0.2pm nchannel MOSFETs) to the VT roll-off and DIBL in subquarter micron NMOSFETs. This B redistribution originates mainly from ion implantation damage in the source and drain. IntroductionThe reduction of the channel length greatly improves the current driving capability of MOSFETs and allows to increase

The importance of testing approaches that exploit error tolerance to improve yield has previously been established. Error rate, defined as the percentage of vectors for which the value at a circuit's output deviates from the corresponding error-free value, has been identified as a key metric for severity. In error-rate testing every chip that has an error rate greater than or equal to a threshold specified by the application is unacceptable for the application and discarded; all other chips are acceptable. The objective of error-rate testing is to reject every unacceptable chip while accepting all (or a maximum number) of the acceptable chips.We previously showed that it is not always possible to generate a test set that detects all unacceptable faults, i.e., faults that cause an error rate greater than or equal to the threshold error rate, without detecting some of the acceptable faults, i.e., faults that cause an error rate less than the threshold.In this paper, we introduce the new notion of multi-vector testing and prove that this notion enables us to detect all unacceptable faults without detecting any of the acceptable faults. We derive an upper bound on the size of such a test for a general case. As this universal bound can be large in some cases, we use a structural approach and find much tighter upper bounds for special classes of circuits. Experiments on benchmark circuits show that the required test-sizes for arbitrary circuits are much lower than our universal bounds, and practically useful.