A Room Temperature 0.1 /spl mu/m CMOS on SOI

Shahidi,; Blair,; Beyer,; Bucelot,; Buti,; Chang,; Chu, Xiaowen; Coane,; Comfort,; Davari,; Dennard,; Furkay,; Hovel,; Johnson, _______; Klaus,; Kiewtniack,; Logan, Stuart; Lii,; McFarland,; Mazzeo, Antonino; Moy,; Neely,; Ning,; Rodríguez,; Sadaria,; Stiffier,; Sun, Dong; Warnock,

doi:10.1109/vlsit.1993.760228

Cited by 24 publications

(9 citation statements)

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“…This is illustrated in Fig. 6 [8]: When the device becomes fully depleted threshold voltage changes as a function of body (film) thickness. Scaling down the nodes increases the doping and therefore V T variation: As one scales the technology to the future nodes, the fully-depleted device body thickness has to be reduced (to help with SCE).…”

Section: -Multiple-v T Setting In 3d Fullydepleted Devicesmentioning

confidence: 99%

From 2D-planar to 3D-non-planar device architecture: A scalable path forward?

Shahidi

2013

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference

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The microelectronics industry is in the process of transitioning from 2D-planar devices to 3D-non-planar (FinFET). In this paper, a metric is developed to assess the impact of scaling and device performance on chip (circuit) power as it is migrated node-to-node. The impact of node migration is assessed at product level as it is moved from 32 nm (2D-planar) to 22 nm (3D-non-planar device). Some of the limitations of the existing 22 nm 3D-device is reviewed that may explain some of the short comings in the product performance. Going forward it is critical that in two areas the FinFET needs to be improved: Multi-V T implementation and move away from the tapered fin shape.

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Section: -Multiple-v T Setting In 3d Fullydepleted Devicesmentioning

confidence: 99%

From 2D-planar to 3D-non-planar device architecture: A scalable path forward?

Shahidi

2013

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference

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“…improvement is only caused by the reduction in junction depth. As shown in Figure 4, if the junction depth in bulk Si is the same as the SOI film thickness, the V T roll-off in bulk Si and SOI is the same [2]. It has been shown that for a given channel length, FD SOI devices exhibit increased short-channel effects (SCE) compared to partially depleted SOI unless the silicon film thickness becomes much smaller than the depletion depth [8].…”

Section: Figurementioning

confidence: 99%

“…Threshold-voltage roll-off for bulk Si and SOI of various thicknesses, t SOI , at a film doping of 2 ϫ 10 17 for 0.1-m devices with gate-oxide thickness, t OX , of 7 nm. Reproduced with permission from [2]; © 1994 IEEE.…”

Section: Figurementioning

confidence: 99%

“…In early 1989, the IBM Research Division initiated activity in SOI CMOS with a program focusing on device design and materials research. The results of this early work were the adoption of the partially depleted device design point, the demonstration of a 0.1-m effectivechannel-length (L EFF ) CMOS [2], its application to a 512Kb SRAM, significant progress in methodology to characterize the floating-body effects, and notable progress in SIMOX (Separation by IMplantation of OXygen) materials technology which was developed on 5-in. wafers.…”

Section: Introductionmentioning

confidence: 99%

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SOI technology for the GHz era

Shahidi

2002

IBM J. Res. & Dev.

174

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Silicon-on-insulator (SOI) CMOS offers a 20-35% performance gain over bulk CMOS. High-performance microprocessors using SOI CMOS have been commercially available since 1998. As the technology moves to the 0.13-m generation, SOI is being used by more companies, and its application is spreading to lower-end microprocessors and SRAMs. In this paper, after giving a short history of SOI in IBM, we describe the reasons for performance improvement with SOI, and its scalability to the 0.1-m generation and beyond. Some of the recent applications of SOI in high-end microprocessors and its upcoming uses in low-power, radio-frequency (rf) CMOS, embedded DRAM (EDRAM), and the integration of vertical SiGe bipolar devices on SOI are described. As we move to the 0.1-m generation and beyond, SOI is expected to be the technology of choice for system-on-a-chip applications which require high-performance CMOS, low-power, embedded memory, and bipolar devices.

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“…Therefore, it was decided to illustrate and verify the nonlinear variance equation using the threshold voltage. The device chosen for examination was the 0.1-m SOI NMOS device developed by IBM [7]- [10] due to the sensitivity of the threshold voltage to the SOI process. The thicknesses of the active top silicon layer (T Si ) and the gate length (L g ) were selected as the two independent input processing parameters because they were found as the dominant sources of threshold voltage fluctuations.…”

Section: Applicationmentioning

confidence: 99%

Derivation of a nonlinear variance equation and its application to SOI technology

Rowlands

Dimitrijev

2000

IEEE Trans. Semicond. Manufact.

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An analytic nonlinear equation for variance was derived along with a method based on response surface mapping techniques to calculate the variance using the proposed equation. The technique was applied to the threshold voltage of a 0.1-m silicon-on-insulator MOS device, and the variance value obtained was verified using Monte Carlo simulation. The threshold voltage dependence upon active-layer thickness was found to be highly nonlinear due to the device's going from the fully depleted to the partially depleted regime. Analysis of the variance showed that the effect of the nonlinear terms (18.7%) is more important than the effect of the mixed term (0.7%) and almost as important as the contribution of the second most dominant input-process parameter (23.6%). This illustrates the importance of the proposed nonlinear equation.

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A Room Temperature 0.1 /spl mu/m CMOS on SOI

Cited by 24 publications

References 0 publications

From 2D-planar to 3D-non-planar device architecture: A scalable path forward?

From 2D-planar to 3D-non-planar device architecture: A scalable path forward?

SOI technology for the GHz era

Derivation of a nonlinear variance equation and its application to SOI technology

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