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Several state-of-the-art monitoring and control systems, such as dc motor controllers, power line monitoring and protection systems, instrumentation systems, and battery monitors, require direct digitization of high-voltage (HV) input signals. Analog-to-digital converters (ADCs) that can digitize HV signals require high linearity and low-voltage coefficient capacitors. A built-in self-calibration and digital-trim algorithm correcting static mismatches in capacitive digital-to-analog converter (DAC) used in successive approximation register analog-todigital converters (SAR ADCs) is proposed. The algorithm uses a dynamic error correction (DEC) capacitor to cancel the static errors occurring in each capacitor of the array as the first step upon power-up and eliminates the need for an extra calibration DAC. Self-trimming is performed digitally during normal ADC operation. The algorithm is implemented on a 14-bit HV input range SAR ADC with integrated DEC capacitors. The IC is fabricated in 0.6-µm HV-compliant CMOS process, accepting up to 24V pp differential input signal. The proposed approach achieves 73.32-dB signal-to-noise and distortion ratio, which is an improvement of 12.03 dB after self-calibration at 400-kS/s sampling rate, consuming 90 mW from a ±15 V supply. The calibration circuitry occupies 28% of the capacitor DAC and consumes <15 mW during operation. Measurement results show that this algorithm reduces integral nonlinearity from as high as 7 LSBs down to 1 LSB, and it works even in the presence of larger mismatches exceeding 260 LSBs. Similarly, it reduces differential nonlinearity errors from 10 LSBs down to 1 LSB. The ADC occupies an active area of 9.76 mm 2 .

A radix-3, 4-trits, Ternary Successive Approximation Analog to Digital Converter (TSAR-ADC), with an option to extend to radix-N approaches is presented. Proposed TSAR-ADC architecture generates 4 ternary outputs spanning 3 4 =81 binary levels linearly for a rail-to-rail input voltage ranging from 0 to 3.3V. The radix-3 TSAR-ADC takes only 4 clock cycles for producing 4-trits or 6.33 bits in comparison to 7 clock cycles in a conventional binary SAR converter. The ADC is designed and fabricated on a 0.35µm double poly, three level metal CMOS technology, achieving less than 1 LSB INL, 0.8 LSB of DNL, consuming 1.6-mW from a 3.3-V supply.

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