This paper deals with the performance of both gate and drain control coefficients to analyze the behavior of carbon nanotube field effect transistors (CNTFETs) under ballistic conditions and based on the change of different parameter value, such as oxide thickness of structure and temperature variation. A thorough study of both gate and drain control coefficient effects on the performance of CNTFETs has been conducted under different temperature and oxide layers and the output of the device has been analyzed through different parameters. Higher values of control coefficient help to attain larger transconductance by the increasing temperatures. For a fixed value of control coefficient, 4[Formula: see text]nm thickness of oxide has a transconductance of [Formula: see text] 4.5 [Formula: see text] 10[Formula: see text] S/m. Smaller oxide layer thickness has higher slope of increment in transconductance value. ON-state current to leakage current ratio shows a steady state response toward increment of gate control coefficient. Also, increment of oxide thickness has an adverse effect on current ratio, while a linear decay of current ratio is observed with the increased value of drain controlled one. Drain-induced battery lowering (DIBL) effect decreases with the value of gate control one and increases with the drain control coefficient. In this way, the optimum value for both the control coefficients has to be considered in order to perform well.
Molecular dynamics (MD) simulations have been applied to study mobilities of Σ3, Σ7 and Σ11 grain boundaries in CdTe. First, an existing MD approach to drive the motion of grain boundaries in face-centered-cubic and body-centered-cubic crystals was generalized for arbitrary crystals. MD simulations were next performed to calculate grain boundary velocities in CdTe crystals at different temperatures, driving forces, and grain boundary terminations. Here a grain boundary is said to be Te-terminated if its migration encounters sequentially C d · T e − C d · T e … planes, where “·” and “−” represent short and long spacing respectively. Likewise, a grain boundary is said to be Cd-terminated if its migration encounters sequentially T e · C d − T e · C d … planes. Grain boundary mobility laws, suitable for engineering time and length scales, were then obtained by fitting the MD results to Arrhenius equation. These studies indicated that the Σ3 grain boundary has significantly lower mobility than the Σ7 and Σ11 grain boundaries. The Σ7 Te-terminated grain boundary has lower mobility than the Σ7 Cd-terminated grain boundary, and that the Σ11 Cd-terminated grain boundary has lower mobility than the Σ11 Te-terminated grain boundary.
Grain structures impact the performance of semiconductor devices. Molecular dynamics has been successfully applied to simulate the growth of semiconductor compounds, reproducing the experimentally observed complex zincblende and wurtzite grains. However, methodologies to characterize the simulated grain structures are still not mature, especially for semiconductors. This limits the usefulness of simulations in material optimization. In this work, the grain tracking algorithm originally developed by Panzarino et al. has been utilized to analyze the CdTe/CdS films obtained from molecular dynamics simulations. This work demonstrates that the parameters obtained from the polyhedral template matching algorithm in OVITO can be used to calculate the orientation of each grain. This provides a variety of useful information such as grain domains, grain orientations, plane indices, and sample texture. Moreover, dynamic analysis of microstructure evolution can be performed to understand grain growth mechanisms and kinetics. There are other useful features that are not included in the current tool such as identification and tracking of point defects (especially vacancies at grain boundaries). Nonetheless, the current approach is useful and our CdTe/CdS results provide input for further computational studies to relate grain structures to physical, chemical, mechanical, and electronic properties.
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