Security ICs are vulnerable to side-channel attacks (SCAs) that find the secret key by monitoring the power consumption or other information that is leaked by the switching behavior of digital CMOS gates. This paper describes a side-channel attack resistant coprocessor IC fabricated in 0.18-m CMOS consisting of an Advanced Encryption Standard (AES) based cryptographic engine, a fingerprint-matching engine, template storage, and an interface unit. Two functionally identical coprocessors have been fabricated on the same die. The first coprocessor was implemented using standard cells and regular routing techniques. The second coprocessor was implemented using a logic style called wave dynamic differential logic (WDDL) and a layout technique called differential routing to combat the differential power analysis (DPA) side-channel attack. Measurement-based experimental results show that a DPA attack on the insecure coprocessor requires only 8000 encryptions to disclose the entire 128-bit secret key. The same attack on the secure coprocessor does not disclose the entire secret key even after 1 500 000 encryptions.

Abstract. Wave dynamic differential logic combined with differential routing is a working, practical technique to thwart side-channel power attacks. Measurement-based experimental results show that a differential power analysis attack on a prototype IC, fabricated in 0.18µm CMOS, does not disclose the entire secret key of the AES algorithm at 1,500,000 measurement acquisitions. This makes the attack de facto infeasible. The required number of measurements is larger than the lifetime of the secret key in most practical systems.

In this paper, we present a novel secure iris verification system, where a transformed version of the iris template instead of the plain reference is stored for protecting the sensitive biometric data. An Error Correcting Code (ECC) technique is adopted to perform the comparison in the transformed domain. A two-segment method is proposed to execute the feature verification, where a Bose-Chaudhuri-Hochquenghem (BCH) code of a random bit-stream is introduced to eliminate the considerable differences between the features extracted from different scans of irises. A reliable bits selection process during the iris feature generation stage reduces the system error rate from 6.0% to 0.8%. The appropriate size of the set of reliable bits is determined by investigating the best match between the associated error correct cutting edge and the actual verification accuracy.

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In this paper, we propose a novel robust secure fingerprint matching technique, which is secure against side channel attacks. An algorithm based on the local structure of the minutiae is presented to match the fingerprints. The main contribution is the careful division of the fingerprint recognition system into two parts: a secure part and a non-secure part. Only the relative small secure part, which contains sensitive biometric template information, requires realization in specialized DPA-proof logic. The rest of the system is running on LEON, which is a regular embedded platform.