AES-Based Security Coprocessor IC in 0.18-&amp;lt;tex&amp;gt;$muhbox m$&amp;lt;/tex&amp;gt;CMOS With Resistance to Differential Power Analysis Side-Channel Attacks

Hwang, D.; Tiri, Kris; Hodjat, A.; Lai, Bo-Cheng; Yang, Shenglin; Schaumont, Patrick; Verbauwhede, Ingrid

doi:10.1109/jssc.2006.870913

Cited by 142 publications

(69 citation statements)

References 11 publications

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“…An implementation of a WDDL AES coprocessor, in a 0.18μm 1.8V CMOS technology, was proposed in [9]. It costs a 3 times increase in area, a 3.8 times decrease in throughput and a 3.7 times increase of the power consumption at 50 MHz, compared to its static CMOS counterpart.…”

Section: Previous Workmentioning

confidence: 99%

Information Theoretic and Security Analysis of a 65-Nanometer DDSLL AES S-Box

Renauld

Kamel

Standaert

et al. 2011

Cryptographic Hardware and Embedded Systems – CHES 2011

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Abstract. In a recent work from Eurocrypt 2011, Renauld et al. discussed the impact of the increased variability in nanoscale CMOS devices on their evaluation against side-channel attacks. In this paper, we complement this work by analyzing an implementation of the AES S-box, in the DDSLL dual-rail logic style, using the same 65-nanometer technology. For this purpose, we first compare the performance results of the static CMOS and dual-rail S-boxes. We show that full custom design allows to nicely mitigate the performance drawbacks that are usually reported for dual-rail circuits. Next, we evaluate the side-channel leakages of these S-boxes, using both simulations and actual measurements. We take advantage of state-of-the-art evaluation tools, and discuss the quantity and nature (e.g. linearity) of the physical information they provide. Our results show that the security improvement of the DDSLL S-box is typically in the range of one order of magnitude (in terms of "number of traces to recover the key"). They also confirm the importance of a profiled information theoretic analysis for the worst-case security evaluation of leaking devices. They finally raise the important question whether dual-rail logic styles remain a promising approach for reducing the side-channel information leakages in front of technology scaling, as hardware constraints such as balanced routing may become increasingly challenging to fulfill, as circuit sizes tend towards the nanometer scale.

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Section: Previous Workmentioning

confidence: 99%

Information Theoretic and Security Analysis of a 65-Nanometer DDSLL AES S-Box

Renauld

Kamel

Standaert

et al. 2011

Cryptographic Hardware and Embedded Systems – CHES 2011

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“…In [12], wave dynamic differential logic circuit with regular routing algorithm is exploited to equalize the current between rising and falling transitions. However, at least double hardware latency, area cost, and energy for unprotected encryption engines are required due to precharging for half cycle, and generating complementary logic outputs from divided single ended modules with equivalent power consumption.…”

Section: Introductionmentioning

confidence: 99%

An Efficient Countermeasure against Correlation Power-Analysis Attacks with Randomized Montgomery Operations for DF-ECC Processor

Lee

Chung

Chang

et al. 2012

Cryptographic Hardware and Embedded Systems – CHES 2012

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Abstract. Correlation power-analysis (CPA) attacks are a serious threat for cryptographic device because the key can be disclosed from data-dependent power consumption. Hiding power consumption of encryption circuit can increase the security against CPA attacks, but it results in a large overhead for cost, speed, and energy dissipation. Masking processed data such as randomized scalar or primary base point on elliptic curve is another approach to prevent CPA attacks. However, these methods requiring pre-computed data are not suitable for hardware implementation of real-time applications. In this paper, a new CPA countermeasure performing all field operations in a randomized Montgomery domain is proposed to eliminate the correlation between target and reference power traces. After implemented in 90-nm CMOS process, our protected 521-bit dual-field elliptic curve cryptographic (DF-ECC) processor can perform one elliptic curve scalar multiplication (ECSM) in 4.57ms over GF (p 521 ) and 2.77ms over GF (2 409 ) with 3.6% area and 3.8% power overhead. Experiments from an FPGA evaluation board demonstrate that the private key of unprotected device will be revealed within 10 3 power traces, whereas the same attacks on our proposal cannot successfully extract the key value even after 10 6 measurements.

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“…For example, the Smart Card software is developed on fixed hardware platforms, so the results in that area are software-based solutions. At the same time, many special circuit styles [32,33] have been developed to address PA at the hardware level. Such circuitlevel solutions are treated independently from the software-level solutions.…”

Section: Introductionmentioning

confidence: 99%

Programmable and Parallel ECC Coprocessor Architecture: Tradeoffs between Area, Speed and Security

Guo

Fan

Schaumont

et al. 2009

Lecture Notes in Computer Science

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Abstract. Elliptic Curve Cryptography implementations are known to be vulnerable to various side-channel attacks and fault injection attacks, and many countermeasures have been proposed. However, selecting and integrating a set of countermeasures targeting multiple attacks into an ECC design is far from trivial. Security, performance and cost need to be considered together. In this paper, we describe a generic ECC coprocessor architecture, which is scalable and programmable. We demonstrate the coprocessor architecture with a set of countermeasures to address a collection of side-channel attacks and fault attacks. The programmable design of the coprocessor enables tradeoffs between area, speed, and security.

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AES-Based Security Coprocessor IC in 0.18-<tex>$muhbox m$</tex>CMOS With Resistance to Differential Power Analysis Side-Channel Attacks

Cited by 142 publications

References 11 publications

Information Theoretic and Security Analysis of a 65-Nanometer DDSLL AES S-Box

Information Theoretic and Security Analysis of a 65-Nanometer DDSLL AES S-Box

An Efficient Countermeasure against Correlation Power-Analysis Attacks with Randomized Montgomery Operations for DF-ECC Processor

Programmable and Parallel ECC Coprocessor Architecture: Tradeoffs between Area, Speed and Security

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