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We describe the investigation of epitaxial SrTiO 3 /BaTiO 3 strained superlattice films prepared by an atomic-layer metalorganic chemical vapor deposition (ALMOCVD) method. Transmission electron microscopy (TEM) observation shows that the multilayered structure is globally uniform and that the interfaces formed between the different layers are of low roughness. Xray diffraction (XRD) analysis reveals a series of satellite peaks on both sides of the zero-order peak, a characteristic feature of the superlattice structure. Careful analysis of XRD and HRTEM images suggests that the tetragonality in the superlattice films is enhanced; this is presumably due to strain caused by heteroepitaxial growth. Dielectric constants of the superlattice films increase with decreasing period of the superlattice structure. An equivalent oxide thickness of 0.8 nm is obtained. These results demonstrate that the ferroelectricity of SrTiO 3 /BaTiO 3 superlattice films can be controlled artificially by fixing the period of the superlattice.

A new method for the fabrication of nanocrystalline silicon (nc-Si) in SiH 4 plasma with very-high-frequency (VHF; 144MHz) excitation is proposed to increase the deposition rate, to control the size, and to minimize size dispersion of nc-Si. Nanocrystalline silicon is formed in the gas phase of the SiH 4 plasma cell by coalescence of radicals. Supplying Ar enhances the nucleation of nc-Si because of high efficiency of SiH 4 excitation into SiH 2 radicals resulting in the nucleation. The deposition rate is thus increased by a factor of 100 to 10 12 /cm 2 h. At the low flow rate of SiH 4 , smaller nc-Si with small dispersion is obtained. Moreover, when pulsed-SiH 4 is supplied into Ar plasma, the growth of nuclei is limited by the time when SiH 4 flows. The size of nc-Si and its dispersion are adjusted by the duration of SiH 4 gas pulse.

The room-temperature operation of a single-electron narrow-channel memory device has been demonstrated by the combined fabrication of a narrow-channel (20 nm wide by 80 nm long) field-effect transistor (FET) defined by electron-beam lithography and nanocrystalline Si (nc-Si) dots formed by annealing a thin film of SiO x (x<2). Electrons are injected into nc-Si floating gate dots in discrete units, as observed by the stepwise increase in the threshold shift with writing bias, which is expected for Coulomb repulsion within the nc-Si dot. Time-dependent measurement of the channel current under the floating gate shows stepwise loss of charge, with a lifetime of each stored electron of about 500 s at room temperature. Measurements at low temperature (20 K) show similar discrete steps in memory writing.

Multiple-tunnel-junction-based nonvolatile single-electron-memory devices are promising for fast write/erase operation and long retention time. Fabrication of multiple-tunnel junctions with a predetermined number of barriers and islands is a major problem in realizing such devices. We have fabricated multiple-tunnel-junction-based single-electron devices by an electron-beam direct writing technique in a silicon-on-insulator layer. Using this technique, it is possible to fabricate multiple ultrasmall islands and tunnel barriers at a predetermined position, which is very important for reproducible device characteristics. Single-electron-memory devices based on multiple-tunnel junctions are fabricated. In these devices, a multiple-tunnel junction connects the gate electrode and a storage island. The Coulomb blockade across the multiple-tunnel junction acts as an energy barrier. Single-electron-memory operation is observed at 20 K. Retention time of at least 4 h has been observed.