The temperature dependence of the conduction mechanism in thin films of ϳ8 nm diameter silicon nanocrystals is investigated using Al/ Si nanocrystal/ p-Si/ Al diodes. A film thickness of 300 nm is used. From 300 to 200 K, space charge limited current, in the presence of an exponential distribution of trapping states, dominates the conduction mechanism. Using this model, a trap density N t = 2.3 ϫ 10 17 cm −3 and a characteristic trap temperature T t = 1670 K can be extracted. The trap density is within an order of magnitude of the nanocrystal number density, suggesting that most nanocrystals trap single or a few carriers at most.

We investigate the temperature dependence of conduction in size-controlled silicon nanocrystals. The nanocrystals are ϳ8 nm in diameter, covered by ϳ1.5 nm thick SiO 2 shells. In 300 nm thick films for temperatures T from 30 to 200 K, the conductivity follows a ln͑͒ vs 1 / T 1/2 dependence. This may be associated with either percolation-hopping conductance or Efros-Shklovskii variable range hopping. Assuming hopping sites only on the nanocrystals, the data agree well with the percolation model.

A model to describe the underlying physics of high-energy electron emission from a porous silicon diode is presented. The model is based on an atomistic tight-binding method combined with semiclassical Monte Carlo simulation. It well reproduces essential features of experimental findings. An initial acceleration region is shown to play a crucial role in generating quasiballistic electron emission. © 2011 American Institute of Physics. ͓doi:10.1063/1.3553501͔ Nanocrystalline silicon ͑nc-Si͒, crystalline silicon with a size below several nanometers, shows characteristic of electronic and photonic effects originated in strong quantum confinement of electrons. These effects have been applied to numerous device applications. 1,2 One of the important applications is a surface-emitting diode, 3 whose active region consists of porous Si ͑PS͒ comprising treelike network of nc-Si dots. When high voltage is applied to a PS diode, electrons are quasiballistically emitted from the diode surface. In spite of the fact that high-energy electron emission from a PS diode is clearly observed, the detailed mechanism has not been fully understood and explained. One of the difficulties associated with theoretical analysis of the high-energy electron emission is due to coexistence of the strong quantum confinement in nc-Si dots and semiclassical hot-electron transport under high bias condition. In this letter, we present a model 4 to capture the essential experimental features of the quasiballistic electron emission. Our model is based on an atomistic tight-binding method combined with semiclassical Monte Carlo simulation, which enables us to treat the quantum confinement and the high-energy transport in a unified manner.We consider a PS diode whose schematic diagram is given in Fig. 1͑a͒. The active region of ϳ1 m in length consists of nc-Si dots connected through thin SiO 2 layers. The typical size of a nc-Si dot is ϳ4 nm in diameter, and the oxide thickness is ϳ1 nm. When a positive bias voltage V ps is applied to the thin Au electrode with respect to the n-type Si substrate, electrons are emitted from the surface. As schematically shown in Fig. 1͑b͒, major voltage drop occurs across the PS region due to its high resistivity. The energy distribution of the emitted electrons has been measured in various device structures with different fabrication processes. From the measured distribution and by considering the Au work function, the energy loss of the emitted electrons, E loss , has been obtained, which indicates that electrons quasiballistically travel through the active region.The experimental features of the energy loss, E loss , described in Refs. 1 and 5 can be summarized as follows: ͑1͒ E loss ͑Ϸ10 eV͒ is nearly independent of V ps for 10 V Շ V ps Շ 30 V; ͑2͒ E loss can vary from sample to sample but is a virtually constant parameter of each individual device; and ͑3͒ E loss becomes smaller when temperature is lowered from room temperature to low temperature ͑T = 100 K͒.Our model for the quasiballistic transport through a PS d...

Abstract-A polycrystalline-silicon thin-film transistor (TFT), with a single grain boundary (GB) present in the channel, is simulated using two-dimensional numerical simulation, which includes a model of deep trap states at GBs. It is observed that the potential barrier resulting from a GB in the channel acts to suppress current flowing through the channel when the barrier height is greater than the thermal voltage. The conduction mechanism in the subthreshold regime is clarified. The turn-on characteristics of the device are controlled primarily by gate-induced grain barrier lowering as opposed to modulation of carriers in the channel by the gate voltage. In the negative bias region it is found that suppression of the off current is aided by the GB potential barrier. Scaling of the various geometrical parameters of the device are investigated. Improved subthreshold characteristics, compared to an equivalent silicon-on-insulator (SOI) structure, are found for aggressively scaled devices, due to the presence of a GB in the channel.