Threshold voltage instability measured by the pulse current-voltage technique has been recognized as the transient charging and discharging of the preexisting bulk traps in Hf-based high-k gate dielectrics, and these high-k traps or called border traps can instantly exchange charge carriers with the underlying Si substrate by tunneling through the thin interfacial oxide. Based on an elastic tunneling model through trapezoidal potential barriers, the spatial and energetic distribution of border traps in the HfO2∕SiO2 high-k gate stack can be profiled as a smoothed, three-dimensional mesh by measuring the low-frequency capacitance-voltage characteristics of high-k metal-oxide-semiconductor capacitors with n-type Si substrate.

Impurity concentration profiles of arsenic ion implantation in sputtered and chemical vapor deposited (CVD) tungsten layers are studied. Arsenic impurity profiles in tungsten and silicon are measured using Rutherford backscattering and secondary ion mass spectrometries. Projected range and projected range straggle for both layers are obtained from these profiles. A smaller projected range straggle, indicating narrower impurity profiles is attained in the CVD layer when compared with that in sputtered layer. However, these values are much greater than those predicted by the LSS theory. Profile tailing appearing at lower concentrations in through tungsten implantation is also studied from carrier concentration profile measurement in silicon. Profile tailing appearing at low concentrations is specifically evident in sputtered layers. However, it does not appear in the CVD layer. Since the penetration of ion implanted species can be suppressed markedly in the CVD tungsten layer, this layer is a promising material for the self-aligned gate process.Ion implantation in tungsten is being looked at as an important approach in the self-aligned gate process. However, few papers have reported on implantation in tungsten (1-3). Impurity profile measurements in tungsten cannot easily be carried out by Rutherford backscattering spectrometry (RBS) measurement, because the observed spectra of ion implanted species overlap with that of tungsten (4). Impurity profile calibration is needed in secondary ion mass spectrometry (SIMS) measurement.Computer simulation has produced an optimized layer structure without spectrum overlapping (4). The measurement for the optimized layer gives exact impurity profiles in tungsten employing RBS. Iwata et al. (5) reported a sputtered tungsten gate process, where penetration of ion-implanted species through W/SiOJSi was observed by SIMS. It has been reported that chemically vapor deposited (CVD) tungsten shows better thermal stability (6-8). Recently, selective tungsten deposition by CVD for via contact holes has been studied by many authors (9-11). Ion implantation is an important process in the ohmic contact application as well as in the selfaligned gate process. However, few papers have reported ion implantation in CVD tungsten.Delfino and DeBlasi (2) studied B and BF2 implantation in silicon through ll0A thick selective tungsten films. Carrier concentration profiles in silicon were observed. They reported sufficient stopping power and an ineffectiveness in eliminating axial boron channeling (3, 12) Tsaur et al. (12) studied the formation of selective tungsten silicide by arsenic ion beam mixing, employing rapid thermal annealing.A study of the ion implantation profile in tungsten, and determination of projected range Rp and projected range straggle ARp, which are required in th}s application, have not yet been reported.This paper describes ion implantation in sputtered and CVD tungsten layers. Arsenic impurity profiles in tungsten and silicon observed by RBS and SIMS are shown. Experimental Pro...