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This paper presents design of the low power RF transceiver [1] which is suitable for wireless sensor network. Using 5.8 GHz band has potentiality to achieve small size wireless sensor module because of smaller antenna in higher frequency. The proposed transceiver utilizes different modulation schemes for uplink and downlink to optimize power consumption and spectral efficiency. In addition, supply voltage of 0.5V can reduce the power consumption of overall RF transceiver. The prototype transceiver was fabricated in 65nm CMOS process, and the transmitter achieved EVM of 12.6% while consuming 2.86mW, and the receiver realizes sensitivity of -75dBm while consuming 0.83mW. I. INTRODUCTIONWireless sensor network (WSN) has recently drawn big attention because it can achieve safe and reliable society. To construct WSN, wireless sensor nodes featuring ultra-low-power consumption and small size are required. The former is to reduce the cost of battery exchanges, and the latter is to arrange a lot of modules in required field. Using higher frequency-band is suitable for small size module because of smaller antenna, however, this causes higher power consumption. Low-voltage power supply is a common approach to reduce power consumption [2], however, it is quite difficult to achieve low voltage operation in the RF transceiver because of the decreasing maximum operation frequency, SNR, and voltage headroom. In addition, the system planning which allows low power consumption of each module is also important.Thus, we have proposed a 0.5-V 5.8-GHz ultra-low-power asymmetrical RF transceiver in the literature [1], and this paper presents the design of it. The detail of the proposed transceiver is shown in sec.II. Measured results are shown and discussed in sec.III, and this paper is concluded in sec.IV.

This paper presents the RF CMOS transceiver that potentially has the process scalability in terms of area and supply voltage. The proposed transceiver does not contain any inductor and employs inverter-based topology for attaining scalability and large voltage headroom. The prototype transceiver for shortrange communication fabricated in 90 nm Si CMOS process has area of 0.2 mm 2 and achieves 500 Mb/s communication at 1 V supply voltage. The transmitter with the new linearity compensation technique provides EVM of less than −28 dB at −5 dBm output from 0.5 to 2.5 GHz range. The receiver employs active peaking and cherry-hooper techniques and realizes sensitivity of −60 dBm and dynamic range of 50 dB at 1 GHz.