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A novel planar architecture is proposed for tunnel field-effect transistors (TFETs). The advantages of this architecture are exhibited, taking the InAs/Si TFET as an example, and the effects of different device parameters are analyzed in detail. Owing to the gate field being parallel to the tunneling interface, the gate control is enhanced, and a better electrical performance is obtained. Moreover, different from a conventional TFET, in which the effective tunneling area and current can hardly be modulated by the gate length, in our proposed device, the effective tunneling area and current can be adjusted depending on the actual requirements of circuit design, which increases the flexibility of TFET-based circuit design. In addition, the device architecture can also be extended to other materials, such as Ge/Si and GaSb/InAs, and thus be used for both n-type and p-type devices. The results show that the complementary digital inverter structure with InAs/Si as the n-type TFET and Ge/Si as the p-type TFET would be helpful for future ultralow power applications. This proposed structure without any complicated fabrication steps shows better compatibility with CMOS technology compared to other TFETs with heterojunction and structural innovations presented in theoretical works. INDEX TERMS Tunnel field-effect transistor, band-to-band tunneling, InAs/Si heterojunction, complementary TFET inverters.

Turbine blades in aircraft engines may encounter overheating and suffer serious creep property degradation. In this study, the thermal cycling creep experiments were conducted on K465 superalloy under (900 °C/30 min–1100 °C/3 min)/50 MPa, (900 °C/30 min–1150 °C/3 min)/50 MPa and (1000 °C/30 min–1150 °C/3 min)/50 MPa. The investigated thermal cycling creep properties were dramatically degraded, and increasing the overheating temperatures significantly decreased the thermal cycling creep life. The secondary γ′ precipitates obviously dissolved and the area fraction decreased to around 35.2% under (900 °C/30 min–1150 °C/3 min)/50 MPa and (1000 °C/30 min–1150 °C/3 min)/50 MPa, which was almost half that after the standard solution treatment. The decline of the thermal cycling creep properties was mainly due to the significant dissolution of γ′ precipitates. The creep holes/cracks were mainly distributed at the M6C carbides and γ/γ′ eutectics interfaces, M6C carbides and γ′ film interfaces in the grain boundaries, and resulted in the final intergranular fracture.

InP layers grown on Si (001) were achieved by the two-step growth method using gas source molecular beam epitaxy. The effects of growth temperature of nucleation layer on InP/Si epitaxial growth were investigated systematically. Cross-section morphology, surface morphology and crystal quality were characterized by scanning electron microscope images, atomic force microscopy images, high-resolution X-ray diffraction (XRD), rocking curves and reciprocal space maps. The InP/Si interface and surface became smoother and the XRD peak intensity was stronger with the nucleation layer grown at 350 °C. The Results show that the growth temperature of InP nucleation layer can significantly affect the growth process of InP film, and the optimal temperature of InP nucleation layer is required to realize a high-quality wafer-level InP layers on Si (001).

In this paper, an efficient thermal analysis method is presented for large scale compound semiconductor integrated circuits based on a heterojunction bipolar transistor with considering the change of thermal conductivity with temperature. The influence caused by the thermal conductivity can be equivalent to the increment of the local temperature surrounding the individual device. The junction temperature for each device can be efficiently calculated by the combination of the semianalytic temperature distribution function and the iteration of local temperature with high accuracy, providing a temperature distribution for a full chip. Applying this method to the InP frequency divider chip and the GaAs analog to digital converter chip, the computational results well agree with the results from the simulator COMSOL and the infrared thermal imager respectively. The proposed method can also be applied to thermal analysis in various kinds of semiconductor integrated circuits.