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3D heterogeneous integration is an evolving segment in integrated circuit development and advanced packaging to drive More than Moore (MtM) chip scaling. Heterogeneous integration allows IC manufacturers to stack and integrate more silicon devices in a single package, increasing the transistor density and product performance. Product designers seek to gain higher bandwidth, increased power, improved signal integrity, more flexible designs (mix/match different chip functions, sizes, and technology nodes), and lower overall costs. The 3D heterogeneous integration roadmap strives to reduce the bonding bumps/pads pitch to a sub-micrometer level, enabling a higher bump I/O density. Key process development activity is occurring in the wafer-to-wafer (W2W) bonding process to reduce interconnect pitch to 10μm and below. In the W2W process, a wafer bonder is used to align and bond two whole wafers. The bonded wafers are then cut up into stacked chips using a dicing process and undergo testing and further packaging. To successfully unite these two bond surfaces with a very small pitch, tight control of the bond pad alignment is required to make sure the copper pads to be bonded line up perfectly, driving an increased need for overlay metrology precision and die-bonder control. Overlay metrology challenges include thick silicon and tight overlay (OVL) error specifications to enable tight and fast on-product overlay (OPO) control for 3D NAND product development. This work will evaluate the various aspects impacting OPO, including the pre and post-bonding error budget, accuracy, measurability, robustness, and throughput.

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